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AMD-Style ASIC Interview Questions

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  1. Q055Pulse every ninth input eventEasyRTL Design
  2. Q067Flag unknown outputs after resetMediumCDC and Reset
  3. Q071Implement an Eight-Entry Synchronous FIFOMediumTiming
  4. Q074Explain Why a DRAM Read Restores the CellEasyMemory Systems
  5. Q077Choose AXI or APB for a control blockEasyProtocols and Interfaces
  6. Q078Trace an Address Through a Mask ROMEasyMemory Systems
  7. Q090Implement and Verify a Two-Input XOREasyRTL Design
  8. Q109Scoreboard out-of-order GPU wavefront completionHardUVM
  9. Q110Evaluate Four-State Operators with X and ZMediumDesign Verification
  10. Q144Decode IEEE-754 Binary32 and Binary64 EncodingsMediumFirmware
  11. Q151Order the Main Photolithography StepsEasyPhysical Design
  12. Q169Combine Pre-Silicon Checks with FPGA Prototype ValidationMediumDesign Verification
  13. Q172Implement a wrapping four-bit counterEasyRTL Design
  14. Q182Contain unknowns before scan compactionMediumDFT & Physical Design
  15. Q183Decode CPER severity twoEasyPost-Silicon Validation
  16. Q195Build one-write/two-read memory from BRAMMediumRTL Design
  17. Q198Constrain dependent burst fieldsMediumSystemVerilog and UVM
  18. Q265Drive one APB transfer with wait statesMediumUVM
  19. Q332Order the FPGA Build and Bring-Up FlowEasyFirmware
  20. Q333Recognize Testbench-Only Verilog ConstructsEasyDesign Verification
  21. Q342Reorder an eight-packet sequence windowHardComputer Architecture
  22. Q349Co-verify a firmware-programmed DMA ringMediumUVM
  23. Q350Implement a Safe Integer Clock-Enable DividerMediumTiming
  24. Q357Separate combinational behavior from stored stateEasyTiming
  25. Q362Make Mixed Signed Arithmetic ExplicitMediumSV
  26. Q367Distinguish a latch from a flip-flopEasyRTL Design
  27. Q369Predict PN-junction behavior under forward biasEasyPhysical Design
  28. Q374Synchronize and filter an asynchronous alarmMediumCDC and Reset
  29. Q375Parse a bounded RAS error recordHardFirmware & Validation
  30. Q392Calculate and repair setup and hold failuresMediumTiming
  31. Q420Minimize a Four-Input Sum of MintermsMediumRTL Design
  32. Q421Calculate PLL Lock Frequency and Identify Loop RolesMediumTiming
  33. Q447Count errors in a build reportEasyFirmware & Validation
  34. Q457Compare static timing analysis with timing simulationEasyDesign Verification
  35. Q461Choose an analysis port or TLM FIFOEasyUVM
  36. Q475Calculate setup and hold slack with clock latencyMediumTiming
  37. Q478Apply absolute minimum and maximum datapath delaysMediumTiming
  38. Q483Connect a UVM monitor to a scoreboardMediumUVM
  39. Q487Constrain two idle markers in an arrayEasySystemVerilog & UVM
  40. Q491Transfer spaced events with a toggle synchronizerHardClock and Reset Domains
  41. Q513Debug an X after reset releaseMediumDesign Verification
  42. Q545Implement a Flip-Flop Divide-by-2 OutputEasyTiming
  43. Q553Calculate UART 8N1 Frame Time and Payload RateEasyFirmware
  44. Q556Enabled modulo-five counterEasyRTL Design
  45. Q564Bank two writes into one read memoryMediumRTL Design
  46. Q579Implement an Eight-Bit Serial-to-Parallel ConverterMediumRTL Design
  47. Q581Minimize a Three-Input Function with a Don't-CareEasyRTL Design
  48. Q588Implement a Two-Stage Seventeen-Bit Pipelined AdderMediumComputer Architecture
  49. Q590Check independent AXI write channelsMediumAssertions and Formal
  50. Q621Generate a Divide-by-3 Clock with Equal High and Low TimesMediumTiming
  51. Q622Calculate CPI with branch and cache penaltiesMediumComputer Architecture
  52. Q640Order the Steps of a Differential SRAM AccessEasyMemory Systems
  53. Q642Separate CDR Frequency Acquisition from Phase TrackingMediumTiming
  54. Q648Check tagged completion latencyMediumSystemVerilog and UVM
  55. Q668Compare One-, Two-, and Three-Process FSM Coding StylesMediumTiming
  56. Q685Implement a deterministic true dual-port RAMMediumClock and Reset Domains
  57. Q693Explain What Static Timing Analysis ProvesEasyTiming
  58. Q697Choose between an FPGA and a CPLDEasyLow Power
  59. Q699Generate an Unbiased Integer from 10 Through 75EasyDesign Verification
  60. Q703Count consecutive zeros with saturationEasyRTL Design
  61. Q741Explain the move from parallel buses to high-speed serial linksEasyComputer Architecture
  62. Q771Allow AXI address and data reorderingMediumComputer Architecture
  63. Q799Use formal proof with explicit assumptions and coverageMediumFunctional Coverage
  64. Q853Keep a Reference Model Independent Enough to Find RTL BugsMediumDesign Verification
  65. Q855Identify Simulation Defaults for Variables and NetsEasyDesign Verification
  66. Q897Choose an ADC Architecture for Moderate-Speed Low-Power ConversionEasyLow Power
  67. Q898Calculate even parity in post_randomizeEasySV
  68. Q901Classify ECC counter changesMediumPost-Silicon Validation
  69. Q944Separate RTL Design from Independent VerificationEasyDesign Verification
  70. Q948Apply timeunit and timeprecision roundingEasyDesign Verification
  71. Q955Write an eight-bit binary-to-Gray converterEasyMemory Systems
  72. Q960Extend AXI IDs for Two Merged MastersMediumProtocols and Interfaces
  73. Q961Design a dual-clock packet merger architectureMediumClock and Reset Domains
  74. Q973Match a physical-signoff failure to its fixMediumPhysical Design
  75. Q996Stress a page-walk and cache raceMediumComputer Architecture
  76. Q997Prove retention across a power cycleHardLow Power
  77. Q1013Rebudget a Channel from 2 to 3 GHzMediumProtocols and Interfaces
  78. Q1025Choose a low-power technique for a short idle intervalEasyLow Power
  79. Q1028Constrain a proven three-cycle pathMediumTiming
  80. Q1029Floorplan a four-bank SRAM subsystemMediumPhysical Design
  81. Q1033Check CRC retries by transaction IDHardSystemVerilog & UVM
  82. Q1044Choose BRAM copies for two readsEasyComputer Architecture
  83. Q1045Check a 12-bit UVM registerEasySystemVerilog & UVM
  84. Q1064Build a Two-Bank Ping-Pong Frame BufferMediumTiming
  85. Q1067Repair Three Different Clock-Domain CrossingsMediumClock and Reset Domains
  86. Q1068Assert bounded request-to-grant latencyMediumAssertions and Formal
  87. Q1107Derive an Almost-Full Threshold from Stop LatencyHardTiming
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