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AMD-Style ASIC Interview Questions
Filtered interview questions
Showing 88 of 88All questions visible
- Q058DesignOrder the Main Photolithography StepsDesign · Physical designEasy
- Q122DesignExplain What Static Timing Analysis ProvesDesign · STAEasy
- Q156DesignBuild one-write/two-read memory from BRAMDesign · RTLMedium
- Q216Design · ArchImplement a deterministic true dual-port RAMDesign · ArchMediumP
- Q281DesignFloorplan a four-bank SRAM subsystemDesign · SRAMMediumP
- Q303Design · ArchPulse every ninth input eventRTL Design · RTL / MicroarchitectureEasyP
- Q311DesignFlag unknown outputs after resetDesign · CDCMediumP
- Q315DesignImplement an Eight-Entry Synchronous FIFODesign · FIFOMediumP
- Q316Arch · DesignExplain Why a DRAM Read Restores the CellDesign · ArchEasyP
- Q318DesignChoose AXI or APB for a control blockDesign · AXIEasyP
- Q319Arch · DesignTrace an Address Through a Mask ROMDesign · ArchEasyP
- Q329Design · DVImplement and verify a two-input XORDesign · Digital logicEasyP
- Q353DVScoreboard out-of-order GPU wavefront completionDV · ArchHardP
- Q354DV · DesignEvaluate Four-State Operators with X and ZDV · DesignMediumP
- Q378FWDecode IEEE-754 Binary32 and Binary64 EncodingsFW · DesignMediumP
- Q389DV · DesignCombine Pre-Silicon Checks with FPGA Prototype ValidationDV · DesignMediumP
- Q391DesignImplement a wrapping four-bit counterDesign · RTLEasyP
- Q396DesignContain unknowns before scan compactionDesign · DFTMediumP
- Q397FWDecode CPER severity twoSilicon · ReliabilityEasyP
- Q406DVConstrain dependent burst fieldsDV · SystemVerilogMediumP
- Q407DVProve tagged requests return at exact latencyAMD · DVHardP
- Q443DVDrive one APB transfer with wait statesDV · DesignMediumP
- Q492FW · DVOrder the FPGA Build and Bring-Up FlowDV · FWEasyP
- Q493DV · DesignRecognize Testbench-Only Verilog ConstructsDV · DesignEasyP
- Q500ArchReorder an eight-packet sequence windowArch · MicroarchitectureHardP
- Q506DVCo-verify a firmware-programmed DMA ringDV · FWMediumP
- Q507DesignImplement a Safe Integer Clock-Enable DividerDesign · ClockingMediumP
- Q512DesignSeparate combinational behavior from stored stateDesign · ClockingEasyP
- Q517DV · DesignMake Mixed Signed Arithmetic ExplicitDesign · SystemVerilogMediumP
- Q520DesignDistinguish a latch from a flip-flopDesign · Digital fundamentalsEasyP
- Q522DesignPredict PN-junction behavior under forward biasDesign · Semiconductor devicesEasyP
- Q526DesignSynchronize and filter an asynchronous alarmDesign · CDCMediumP
- Q527FWParse a bounded RAS error recordFW · ValidationHardP
- Q538DesignCalculate and repair setup and hold failuresDesign · STAMediumP
- Q562DesignMinimize a Four-Input Sum of MintermsDesign · Logic optimizationMediumP
- Q563DesignCalculate PLL Lock Frequency and Identify Loop RolesDesign · ClockingMediumP
- Q584FWCount errors in a build reportFirmware & ValidationEasyP
- Q593DV · DesignCompare static timing analysis with timing simulationDV · DesignEasyP
- Q597DVChoose an analysis port or TLM FIFODV · DesignEasyP
- Q612DesignCalculate setup and hold slack with clock latencyDesign · STAMediumP
- Q614Design · ArchApply absolute minimum and maximum datapath delaysDesign · ArchMediumP
- Q619DVConnect a UVM monitor to a scoreboardDV · UVMMediumP
- Q622DVConstrain two idle markers in an arraySystemVerilog & UVMEasyP
- Q626DesignTransfer spaced events with a toggle synchronizerDesign · CDCHardP
- Q644DV · DesignDebug an X after reset releaseDV · DesignMediumP
- Q674DesignImplement a Flip-Flop Divide-by-2 OutputDesign · ClockingEasyP
- Q679FWCalculate UART 8N1 Frame Time and Payload RateFW · FirmwareEasyP
- Q682Design · ArchEnabled modulo-five counterRTL Design · RTL / MicroarchitectureEasyP
- Q688Design · ArchBank two writes into one read memoryRTL Design · RTL / MicroarchitectureMediumP
- Q703DesignImplement an Eight-Bit Serial-to-Parallel ConverterDesign · RTLMediumP
- Q705DesignMinimize a Three-Input Function with a Don't-CareDesign · Combinational logicEasyP
- Q712Arch · DesignImplement a Two-Stage Seventeen-Bit Pipelined AdderDesign · ArchMediumP
- Q714DVCheck independent AXI write channelsDV · SVAMediumP
- Q740DesignGenerate a Divide-by-3 Clock with Equal High and Low TimesDesign · ClockingMediumP
- Q741ArchCalculate CPI with branch and cache penaltiesArch · CacheMediumP
- Q761Arch · DesignOrder the Steps of a Differential SRAM AccessDesign · ArchEasyP
- Q763Design · ArchSeparate CDR Frequency Acquisition from Phase TrackingDesign · ArchMediumP
- Q767DVCheck tagged completion latencyDV · SystemVerilogMediumP
- Q782DesignCompare One-, Two-, and Three-Process FSM Coding StylesDesign · FSMMediumP
- Q803DesignChoose between an FPGA and a CPLDDesign · Low powerEasyP
- Q805DV · FWGenerate an Unbiased Integer from 10 Through 75DV · FWEasyP
- Q807DesignCount consecutive zeros with saturationDesign · RTLEasyP
- Q841ArchExplain the move from parallel buses to high-speed serial linksArch · Interconnect architectureEasyP
- Q872ArchAllow AXI address and data reorderingArch · MicroarchitectureMediumP
- Q894DVUse formal proof with explicit assumptions and coverageDV · DesignMediumP
- Q937DV · DesignKeep a Reference Model Independent Enough to Find RTL BugsDV · DesignMediumP
- Q939DV · DesignIdentify Simulation Defaults for Variables and NetsDV · DesignEasyP
- Q981Design · ArchChoose an ADC Architecture for Moderate-Speed Low-Power ConversionDesign · ArchEasyP
- Q982DV · DesignCalculate even parity in post_randomizeDesign · SystemVerilogEasyP
- Q984FWClassify ECC counter changesSilicon · ReliabilityMediumP
- Q1022DV · DesignSeparate RTL Design from Independent VerificationDV · DesignEasyP
- Q1025DVApply timeunit and timeprecision roundingDV · SystemVerilogEasyP
- Q1030Arch · DesignWrite an eight-bit binary-to-Gray converterDesign · Gray codeEasyP
- Q1034Design · ArchExtend AXI IDs for Two Merged MastersDesign · ArchMediumP
- Q1035Design · ArchDesign a dual-clock packet merger architectureDesign · ArchMediumP
- Q1041DesignMatch a physical-signoff failure to its fixDesign · Physical designMediumP
- Q1067ArchStress a page-walk and cache raceArch · CacheMediumP
- Q1068DesignProve retention across a power cycleDesign · Low powerHardP
- Q1081DesignRebudget a Channel from 2 to 3 GHzDesign · Signal integrityMediumP
- Q1090DesignChoose a low-power technique for a short idle intervalDesign · Low powerEasyP
- Q1092DesignConstrain a proven three-cycle pathDesign · STAMediumP
- Q1096DVCheck CRC retries by transaction IDDV · SystemVerilogHardP
- Q1104ArchChoose BRAM copies for two readsComputer Architecture · Architecture / Cache / InterconnectEasyP
- Q1105DVCheck a 12-bit UVM registerSystemVerilog & UVMEasyP
- Q1119Design · ArchBuild a Two-Bank Ping-Pong Frame BufferDesign · ArchMediumP
- Q1122DesignRepair Three Different Clock-Domain CrossingsDesign · CDCMediumP
- Q1123DVAssert bounded request-to-grant latencyDV · SVAMediumP
- Q1159Design · DVDerive an Almost-Full Threshold from Stop LatencyDV · DesignHardP
Study path
AMD-style ASIC interview preparation
Connect timing and RTL implementation with independent verification, memory behavior, architecture, UVM, and physical tradeoffs. Start with cycle behavior, then expose width, latency, ordering, and reset assumptions.
Pair every optimization with a proof plan and quantify the effect on throughput, timing margin, power, or storage. These independent exercises do not describe AMD's official interview process.