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  1. Q064Sort four signed bytes with five compare-swap blocksMediumRTL Design
  2. Q080Match hit-under-miss responses by transaction IDMediumComputer Architecture
  3. Q087Repair a setup path without hiding real uncertaintyHardTiming
  4. Q100DRC versus LVSEasyReliable RTL
  5. Q115Build a parameterized round-robin arbiterMediumArbiters
  6. Q122Fast lookup in a fully associative cacheEasyMemory Systems
  7. Q129Choose a distributed RC model for a long wireMediumTiming
  8. Q131Calculate a falling-to-rising half-cycle setup pathMediumTiming and STA
  9. Q140Little-endian byte orderEasyHardware-Software Integration
  10. Q166Request and acknowledge latency assertionEasyTemporal Checks
  11. Q213Distinguish SC_METHOD from SC_THREADEasySV
  12. Q215UVM polymorphism and virtual dispatchEasySystemVerilog OOP
  13. Q217Find one clock's worst path in a normalized STA reportMediumTiming and STA
  14. Q219Gate-level four-to-one multiplexerEasyCombinational RTL
  15. Q222Check divisibility by five on an LSB-first bit streamMediumStreaming RTL
  16. Q243Detect 1011 with optional overlapMediumFSMs
  17. Q247Synchronous rising-edge detectorEasySequential RTL
  18. Q253Sequence retention, isolation, power switch, and restoreHardLow Power
  19. Q263Check reset-bounded delivery of asynchronous eventsMediumCDC and Reset
  20. Q271Classify a frequency- and voltage-sensitive silicon failureMediumPost-Silicon & Reliability
  21. Q273Latch versus flip-flop behaviorEasyTiming
  22. Q281Meaning of the MOESI Owned stateEasyCoherence
  23. Q289Decode a compact hardware trace streamMediumFirmware
  24. Q305Place-and-route versus clock-tree synthesisEasyClock and Reset
  25. Q317Reason about positive clock skewEasyTiming
  26. Q321Weighted random values without distEasyConstrained Random
  27. Q335Size an asynchronous FIFO from exact event timesMediumClock Domain Crossing
  28. Q348Overlapped versus non-overlapped implication in SVAEasyTemporal Checks
  29. Q354Four-state equality in SystemVerilogEasySV
  30. Q361Avoid VIPT cache synonyms with page-offset indexingMediumMemory Systems
  31. Q385Prove that abort cancels one pending responseMediumAssertions and Formal
  32. Q393Eight-bit equality comparator two waysEasyCombinational RTL
  33. Q400Binary-to-Gray converterEasyClock Domain Crossing
  34. Q411Describe what happens on a demand-page faultEasyMemory Systems
  35. Q416Capture a held multi-bit power-state value across clocksEasyCDC & RDC
  36. Q423Compact duplicate integers without changing first-occurrence orderEasyRTL Design
  37. Q427Drive a complete March C-minus memory testHardDFT & Physical Design
  38. Q437Detect machine endianness in CEasyHardware-Software Integration
  39. Q450Explain why timing needs multiple PVT cornersEasyTiming
  40. Q464UVM factory purposeEasyUVM Components
  41. Q468Peak and achieved memory bandwidthEasyPerformance Analysis
  42. Q469MESI write miss from InvalidEasyCoherence
  43. Q473Combinational versus sequential logicEasyRTL Design
  44. Q479Components of CMOS powerEasyPerformance Analysis
  45. Q481ISR design ruleEasyHardware-Software Integration
  46. Q489Use isolation at a powered-down domain boundaryEasyReliable RTL
  47. Q501Measure dependent L1-cache load latencyHardMemory Systems
  48. Q522Cover opcode, error, and latency combinationsMediumSystemVerilog and UVM
  49. Q525Assert an exact two-cycle responseEasyAssertions & Formal
  50. Q534Track retries in a tagged split-transaction linkHardComputer Architecture
  51. Q576Choose the direct fix for a hold violationEasyTiming
  52. Q597Distinguish IR drop from electromigrationEasyTiming
  53. Q605Why synchronized async-FIFO pointers are conservativeMediumClock Domain Crossing
  54. Q609Take a race-detecting snapshot of an atomic trace ringMediumPost-Silicon Validation
  55. Q611Rank crosstalk delay for three adjacent wiresMediumTiming
  56. Q623First action when coverage misses a targetEasyFunctional Coverage
  57. Q661Four-bit adder and synthesized structureEasyRTL Arithmetic
  58. Q666Explain the value of a two-bit branch predictorEasyMemory Systems
  59. Q680Verify ordered AXI responses with an exact timeoutHardVerification Utilities
  60. Q684Predict how wire width changes R and CMediumTiming
  61. Q718Moore versus Mealy outputsEasyFSMs
  62. Q757Release an asynchronous reset safelyEasyReset Design
  63. Q770Check a byte ALU with an independent scoreboardMediumSystemVerilog & UVM
  64. Q776Why an FSM infers a latchEasyFSMs
  65. Q833Accumulate a four-lane signed dot productMediumRTL Design
  66. Q850Triage an intermittent firmware hang from a crash dumpMediumHardware-Software Integration
  67. Q886Receive 1000 SPI bytes through 256-byte DMA chunksMediumHardware-Software Integration
  68. Q894Choose the operation that exposes a stuck-at-zero SRAM cellEasyPhysical Design and DFT
  69. Q919Place latency in a loosely timed TLM modelEasyMemory Systems
  70. Q925Recover from a speculative memory-order violationMediumMemory Systems
  71. Q927Zero matrix rows and columns in placeMediumFirmware & Validation
  72. Q934X and Z handling in case statementsEasySV
  73. Q936Storage occupied by an unaligned objectEasyFirmware Algorithms
  74. Q943Purpose of regression testingEasyVerification Strategy
  75. Q947Correct CDC method by signal typeEasyClock Domain Crossing
  76. Q952Implement a synchronous FIFO with exact boundary behaviorMediumRTL Design
  77. Q964Find vectors that expose internal stuck-at faultsMediumFormal Verification
  78. Q971Blocking and nonblocking assignment usageEasySV
  79. Q983Generate a 50% duty-cycle divide-by-three clockHardRTL Design
  80. Q995Generate an unbiased integer in an inclusive rangeMediumFirmware Algorithms
  81. Q1031Model memory requests with deterministic orderingHardReference Models
  82. Q1036Test 128 lines for stuck faults and pairwise shortsHardFormal Verification
  83. Q1037Verify a four-lane PCIe deskew bufferHardReference Models
  84. Q1055Check one retained register through a power cycleMediumLow Power Design
  85. Q1075Keep exceptions precise in an out-of-order CPUMediumMemory Systems
  86. Q1077Constrain a balanced six-request descriptor setMediumSystemVerilog & UVM
  87. Q1086Place buffering for glitch-free display scanoutMediumMemory Systems
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