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Apple-Style ASIC Interview Questions
Filtered interview questions
Showing 82 of 82All questions visible
- Q086DesignCapture a held multi-bit power-state value across clocksDesign · CDCEasy
- Q142Design · DVCheck divisibility by five on an LSB-first bit streamDesign · DVMedium
- Q171Design · DVCheck reset-bounded delivery of asynchronous eventsDV · CDCMedium
- Q226Design · DVImplement a synchronous FIFO with exact boundary behaviorDesign · DVMediumP
- Q257DesignSequence retention, isolation, power switch, and restoreDesign · Low powerHardP
- Q309DesignSort four signed bytes with five compare-swap blocksDesign · RTLMediumP
- Q320ArchMatch hit-under-miss responses by transaction IDArch · MicroarchitectureMediumP
- Q326DVMatch out-of-order analysis streams by transaction IDApple · DVHardP
- Q327DesignRepair a setup path without hiding real uncertaintyDesign · STAHardP
- Q340DesignDRC versus LVSDesign · Physical designEasyP
- Q357Design · DVBuild a parameterized round-robin arbiterDesign · DVMediumP
- Q366Design · ArchChoose a distributed RC model for a long wireDesign · ArchMediumP
- Q368DesignCalculate a falling-to-rising half-cycle setup pathDesign · STAMediumP
- Q375FW · ArchLittle-endian byte orderFW · ArchEasyP
- Q388DV · DesignRequest and acknowledge latency assertionDV · DesignEasyP
- Q409ArchDistinguish SC_METHOD from SC_THREADArch · SystemCEasyP
- Q411DVUVM polymorphism and virtual dispatchDV · UVMEasyP
- Q413DesignFind one clock's worst path in a normalized STA reportDesign · STAMediumP
- Q415DesignGate-level four-to-one multiplexerDesign · MuxEasyP
- Q430Design · DVDetect 1011 with optional overlapDesign · DVMediumP
- Q432DesignSynchronous rising-edge detectorDesign · Edge detectorEasyP
- Q449FWClassify a frequency- and voltage-sensitive silicon failureSilicon · ReliabilityMediumP
- Q450DesignLatch versus flip-flop behaviorDesign · LatchEasyP
- Q456Arch · DVMeaning of the MOESI Owned stateArch · DVEasyP
- Q462FWDecode a compact hardware trace streamFW · ValidationMediumP
- Q472DesignPlace-and-route versus clock-tree synthesisDesign · Physical designEasyP
- Q483DesignReason about positive clock skewDesign · STAEasyP
- Q484DVWeighted random values without distDV · SystemVerilogEasyP
- Q495Design · DVSize an asynchronous FIFO from exact event timesDesign · DVMediumP
- Q505DVOverlapped versus non-overlapped implication in SVADV · SVAEasyP
- Q510DV · DesignFour-state equality in SystemVerilogDV · DesignEasyP
- Q516Arch · DesignAvoid VIPT cache synonyms with page-offset indexingArch · DesignMediumP
- Q532DVProve that abort cancels one pending responseDV · SVAMediumP
- Q539DesignEight-bit equality comparator two waysDesign · ComparatorEasyP
- Q545Design · DVBinary-to-Gray converterDesign · DVEasyP
- Q554FW · ArchDescribe what happens on a demand-page faultArch · FWEasyP
- Q565Design · ArchCompact duplicate integers without changing first-occurrence orderRTL Design · RTL / MicroarchitectureEasyP
- Q568DesignDrive a complete March C-minus memory testDesign · DFTHardP
- Q576FWDetect machine endianness in CFW · EndiannessEasyP
- Q587DesignExplain why timing needs multiple PVT cornersDesign · STAEasyP
- Q601DVUVM factory purposeDV · UVMEasyP
- Q605FW · ArchPeak and achieved memory bandwidthArch · FWEasyP
- Q607Arch · DVMESI write miss from InvalidArch · DVEasyP
- Q611DesignCombinational versus sequential logicDesign · Combinational RTLEasyP
- Q617FWISR design ruleFW · InterruptsEasyP
- Q624Design · DVUse isolation at a powered-down domain boundaryDesign · DVEasyP
- Q653DVCover opcode, error, and latency combinationsDV · SystemVerilogMediumP
- Q656DVAssert an exact two-cycle responseAssertions & FormalEasyP
- Q664ArchTrack retries in a tagged split-transaction linkArch · MicroarchitectureHardP
- Q697DVWeighted random without using distApple · DVMediumP
- Q698DVRandomly select unique channelsApple · DVMediumP
- Q701DesignChoose the direct fix for a hold violationDesign · STAEasyP
- Q719DesignDistinguish IR drop from electromigrationDesign · ArchEasyP
- Q726Design · DVWhy synchronized async-FIFO pointers are conservativeDesign · DVMediumP
- Q728FWTake a race-detecting snapshot of an atomic trace ringSilicon · ReliabilityMediumP
- Q731DesignRank crosstalk delay for three adjacent wiresDesign · Physical designMediumP
- Q742DVFirst action when coverage misses a targetDV · Coverage closureEasyP
- Q776Design · ArchFour-bit adder and synthesized structureDesign · ArchEasyP
- Q780ArchExplain the value of a two-bit branch predictorArch · CPUEasyP
- Q793DV · ArchVerify ordered AXI responses with an exact timeoutDV · ArchHardP
- Q796DesignPredict how wire width changes R and CDesign · ArchMediumP
- Q820DesignMoore versus Mealy outputsDesign · FSMEasyP
- Q859Design · DVRelease an asynchronous reset safelyDesign · DVEasyP
- Q871DVCheck a byte ALU with an independent scoreboardSystemVerilog & UVMMediumP
- Q877Design · DVWhy an FSM infers a latchDesign · DVEasyP
- Q925Design · ArchAccumulate a four-lane signed dot productRTL Design · RTL / MicroarchitectureMediumP
- Q978DesignChoose the operation that exposes a stuck-at-zero SRAM cellDesign · DFTEasyP
- Q999ArchPlace latency in a loosely timed TLM modelArch · SystemCEasyP
- Q1006FWZero matrix rows and columns in placeFirmware & ValidationMediumP
- Q1012DV · DesignX and Z handling in case statementsDesign · DVEasyP
- Q1014FW · ArchStorage occupied by an unaligned objectFW · ArchEasyP
- Q1021DVPurpose of regression testingDV · RegressionEasyP
- Q1024Design · DVCorrect CDC method by signal typeDesign · DVEasyP
- Q1038DVFind vectors that expose internal stuck-at faultsDV · DesignMediumP
- Q1040DV · DesignBlocking and nonblocking assignment usageDesign · DVEasyP
- Q1054Design · DVGenerate a 50% duty-cycle divide-by-three clockDesign · DVHardP
- Q1066FWGenerate an unbiased integer in an inclusive rangeFW · DVMediumP
- Q1094DV · ArchModel memory requests with deterministic orderingArch · DVHardP
- Q1099DVTest 128 lines for stuck faults and pairwise shortsDV · DesignHardP
- Q1112DesignCheck one retained register through a power cycleDesign · Low powerMediumP
- Q1132DVConstrain a balanced six-request descriptor setSystemVerilog & UVMMediumP
- Q1142Arch · DesignPlace buffering for glitch-free display scanoutArch · DesignMediumP
Study path
Apple-style ASIC interview preparation
Connect timing closure and memory-system reasoning to concise RTL, CDC, firmware, and hardware-software answers. Explain the state or path first, then the edge case, implementation tradeoff, and evidence you would inspect.
Practice across design and verification: a FIFO, power sequence, or cache decision should include both its timing contract and validation plan. These independent exercises do not describe Apple's official interview process.