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DescriptionQ078

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Q078DesignDVASIC interview problem

Clock-Gating Behavior Checker

TechniquesDVDesignClock gatingEdge correlationScan enable

DifficultyHard

TopicClock and Reset

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Verify that a gated clock emits complete pulses only when functional enable or scan bypass is active. The monitor receives ordered edge callbacks from the reference and gated clocks.

Class declarationSystemVerilog

class ClockGateChecker;
  void on_ref_posedge(bit enable, bit scan_enable);
  void on_ref_negedge(bit enable, bit scan_enable);
  void on_gated_posedge();
  void on_gated_negedge();
  int error_count();
endclass

Example input and output

Use this case to check your interpretation

Input

cycle 0: enable=0
cycle 1: enable rises while source clock is low
cycles 2-3: enable=1
cycle 4: enable falls while source clock is low

Output

gated clock emits complete pulses only during cycles 2-3; no runt pulse at either boundary

Explanation

Latching the enable in the safe clock phase prevents a mid-pulse gate transition.

Requirements (4)

Produce exactly one gated pulse for every enabled reference-clock cycle.
Reject extra gated edges while both enables are low.
Require each gated rising edge to be paired with a falling edge before the next pulse.
Flag enable changes during the unsafe reference-clock phase under the stated latch model.