NVIDIA-Style ASIC Interview Questions

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Showing 122 of 122All questions visible

Q069DesignFind the lowest set laneDesign · RTLEasy
Q146DesignChoose Mealy timing for an immediate matchDesign · RTLEasy
Q193DesignImplement a divide-by-four clock modelDesign · SystemVerilogEasy
Q199ArchBuild a bounded one-producer, one-consumer queueNVIDIA · ArchEasy
Q238Design · DVDesign and verify a round-robin arbiterDesign · DVHardP
Q294Design · DVDetect the wildcard pattern 110?01Design · DVHardP
Q302Design · DVDecide when two-flop synchronization is insufficientDesign · DVMediumP
Q321DesignTrade speed for leakage with multi-Vt cellsDesign · Physical DesignEasyP
Q324DVScoreboard burst-to-single conversionDV · UVMHardP
Q325ArchRecognize LL/SC reservation failureArch · Atomic operationsEasyP
Q333DesignDistinguish clock-group relationship typesDesign · TimingEasyP
Q347DesignRelieve localized routing congestionDesign · Physical DesignEasyP
Q350ArchTrace a GPUDirect RDMA transfer through the platformNVIDIA · ArchMediumP
Q374DVWrite a non-pipelined UVM bus driverDV · UVMMediumP
Q380DVCompare two in-order streams through distinct analysis callbacksNVIDIA · DVMediumP
Q385DVCapture a loop variable in fork...join_noneDV · SystemVerilogMediumP
Q416DesignPeriod after pipelining an OR treeDesign · STAMediumP
Q428DVApply the UVM factory patternDV · UVMEasyP
Q431DesignChoose first-order setup and hold fixesDesign · TimingEasyP
Q442DVBuild a LIFO scoreboardDV · SystemVerilogEasyP
Q445Design · DVSize and verify an asynchronous FIFODesign · DVHardP
Q446FWBuild a recovery plan from GPU error eventsFW · ValidationHardP
Q460DVDesign a two-stage pipelined UVM driverDV · UVMHardP
Q461ArchExplain FlashAttention as an I/O-aware attention algorithmNVIDIA · ArchHardP
Q464Design · ArchProtect a feedthrough across a switchable domainDesign · ArchMediumP
Q466ArchPartition a cache addressArch · CacheMediumP
Q469ArchSend framed messages with nonblocking socketsNVIDIA · ArchMediumP
Q476ArchChoose ring, tree, or hierarchical all-reduceNVIDIA · ArchMediumP
Q477ArchResolve an immediate pipeline data dependencyArch · PipelineEasyP
Q479ArchSelect a topology-local NICNVIDIA · ArchMediumP
Q489ArchPipeline branch prediction and quantify recovery costNVIDIA · ArchHardP
Q490DVInject configuration into a UVM object predictorNVIDIA · DVMediumP
Q494Design · ArchMatch low-power techniques to power componentsDesign · ArchEasyP
Q509DVConstrain one triplicate and seven singletonsDV · SystemVerilogMediumP
Q511DesignFind each scan chain's first failing patternDesign · DFTHardP
Q515DesignCode an active-low asynchronous-reset registerDesign · SystemVerilogEasyP
Q547DV · DesignReason about nonblocking assignment updatesDesign · DVEasyP
Q559Design · ArchCount ones in seven bitsRTL Design · RTL / MicroarchitectureEasyP
Q571DVSerialize concurrent sequences in a four-phase driverNVIDIA · DVMediumP
Q590ArchTwo-to-one weighted arbiterArch · MicroarchitectureMediumP
Q595Design · DVCross a request between powered voltage domainsDesign · DVHardP
Q598ArchImplement a safe registered-memory cacheNVIDIA · ArchHardP
Q602DVDrive one complete four-phase UVM handshakeNVIDIA · DVMediumP
Q604Arch · DesignBalance a pipeline with one added registerArch · DesignMediumP
Q606ArchDebug a collective tail-latency cliff at 1,024 ranksNVIDIA · ArchHardP
Q609Arch · DesignMaintain true LRU state for four waysArch · DesignMediumP
Q620ArchRemove false dependencies in Tomasulo schedulingArch · Out-of-orderMediumP
Q632DVAssert set-dominant fault retentionDV · SVAMediumP
Q646ArchBound a memory-registration cache safelyNVIDIA · ArchMediumP
Q649DVTimestamp exactly 100 rising edgesDV · SystemVerilogEasyP
Q662ArchChoose polling, events, or hybrid progressNVIDIA · ArchMediumP
Q663DesignFind fmax for a half-cycle timing pathDesign · TimingMediumP
Q690DesignHold even decimal counts for an extra enabled cycleNVIDIA · DesignMediumP
Q696DVImplement randc without using randcNVIDIA · DVMediumP
Q708DesignThrottle with temperature hysteresisDesign · Low powerMediumP
Q709DVReplace UVM types without editing the environmentDV · UVMEasyP
Q710Design · ArchXNOR from one 2-to-1 muxRTL Design · RTL / MicroarchitectureEasyP
Q716DVVerify a three-byte serializerDV · ScoreboardHardP
Q733DesignBuild an 8-to-1 mux from 2-to-1 muxesDesign · SystemVerilogEasyP
Q739DesignUse different setup and hold uncertaintyDesign · TimingMediumP
Q751ArchEvict a MOESI Owned line without losing dirty authorityNVIDIA · ArchHardP
Q753DVIdentify the role of a UVM virtual sequenceDV · UVMEasyP
Q758ArchChoose between data-parallel and tensor-parallel shardingNVIDIA · ArchHardP
Q766DesignCheck two synchronized flags for reconvergenceDesign · CDCMediumP
Q791ArchRecognize write-back cache behaviorArch · CacheEasyP
Q797Design · ArchPulse on every adjacent pair of onesRTL Design · RTL / MicroarchitectureEasyP
Q799DesignDetect overlapping 1101 sequencesDesign · SystemVerilogMediumP
Q806DesignExplain the routing antenna effectDesign · Physical DesignEasyP
Q812ArchCompare SIMD execution with SIMT branch divergenceNVIDIA · ArchMediumP
Q816ArchGenerate a ring all-reduce scheduleNVIDIA · ArchHardP
Q824ArchCalculate TLB reach and evaluate huge pagesNVIDIA · ArchMediumP
Q840ArchChoose a GPU training batch size from throughput and memory dataNVIDIA · ArchMediumP
Q845DVVerify a synchronous FIFODV · DesignMediumP
Q847DesignExplain CRPR in a timing reportDesign · TimingEasyP
Q849ArchRemove shared-memory bank conflicts without losing occupancyNVIDIA · ArchHardP
Q851ArchOrder descriptors, doorbells, and remote dataNVIDIA · ArchHardP
Q863DesignTrade ICG granularity for fanout and timingDesign · Physical DesignMediumP
Q864Design · DVConstrain truly unrelated clock domainsDesign · DVEasyP
Q867DesignImplement a parameterized shift registerDesign · SystemVerilogEasyP
Q873DesignConvert between binary and Gray codeDesign · SystemVerilogMediumP
Q878DesignQuarantine traffic after peer resetDesign · CDCMediumP
Q879DesignApply clock skew to setup and holdDesign · TimingEasyP
Q882Design · DVMatch each signal type to a CDC techniqueDesign · DVEasyP
Q883DVConstrain endpoint extrema with a turning interiorNVIDIA · DVMediumP
Q890ArchCheck per-channel link creditsArch · MicroarchitectureHardP
Q896DVSeparate two same-typed analysis streamsNVIDIA · DVHardP
Q908DesignReset state behind a gated clockDesign · ResetMediumP
Q916ArchDiagnose congestion on InfiniBand and RoCENVIDIA · ArchHardP
Q918DVCheck a two-cycle level-valid response pipelineNVIDIA · DVMediumP
Q929DVAssert an exact two-cycle acknowledge edgeNVIDIA · DVHardP
Q931DVConstrain unique extrema and a non-monotonic tailNVIDIA · DVHardP
Q938DesignDetect overlapping five-bit palindromesDesign · SystemVerilogMediumP
Q943DVExplain what functional coverage measuresDV · CoverageEasyP
Q944DesignCompare synchronous and asynchronous resetDesign · SystemVerilogEasyP
Q945ArchQuantify a cache prefetcher's latency and traffic tradeoffNVIDIA · ArchHardP
Q947DVShare a named UVM configuration eventDV · SystemVerilogMediumP
Q957ArchReverse-engineer a sliced shared cacheArch · PerformanceHardP
Q959ArchExplain parallel VIPT lookup and translationArch · Virtual memoryMediumP
Q961ArchAccount for traffic in inclusive and non-inclusive cachesNVIDIA · ArchHardP
Q962Design · ArchSet-dominant sticky fault bitsRTL Design · RTL / MicroarchitectureEasyP
Q964ArchDrain a verbs completion queue safelyNVIDIA · ArchMediumP
Q974DesignTrack parity history with two state bitsDesign · SystemVerilogMediumP
Q979ArchDesign load-store queue forwarding and replayNVIDIA · ArchHardP
Q988DVScore lane returns for one tagged operationDV · SystemVerilogMediumP
Q991DVConstrain mutually exclusive component ownershipDV · SystemVerilogMediumP
Q995DVUse checked down-casting in SystemVerilogDV · SystemVerilogEasyP
Q998DesignChoose always_comb over a manual sensitivity listDesign · SystemVerilogEasyP
Q1013DVSerialize forked automatic workersNVIDIA · DVMediumP
Q1018DVRoute configuration and runtime data between UVM classesNVIDIA · DVMediumP
Q1027Design · DVImplement asynchronous FIFO full and empty logicDesign · DVHardP
Q1039DesignPreserve width through dependent additionsDesign · SystemVerilogEasyP
Q1042DVCheck an incrementing pulse intervalDV · SVAMediumP
Q1047ArchChoose eager or rendezvous from a latency modelNVIDIA · ArchMediumP
Q1057DesignOrder the digital ASIC implementation flowDesign · Physical DesignEasyP
Q1060DesignExplain OCV derates and temperatureDesign · TimingMediumP
Q1071DVCommit forked worker results as one atomic recordNVIDIA · DVMediumP
Q1076ArchReclaim RDMA buffers from queue completionsNVIDIA · ArchMediumP
Q1085DesignIdentify sources of clock uncertaintyDesign · TimingEasyP
Q1102DesignScale distributed-wire delay with lengthDesign · Physical DesignEasyP
Q1115FWBounded byte-string palindrome checkFirmware & ValidationEasyP
Q1121DesignPredict opposite-direction crosstalk delayDesign · Physical DesignEasyP
Q1143FWRespond to a contained uncorrectable ECC errorSilicon · ReliabilityMediumP

Study path

NVIDIA-style ASIC interview preparation

Practice the chain from RTL and SystemVerilog/UVM verification to GPU execution, memory hierarchy, cache coherence, and quantitative performance analysis. Strong answers state assumptions, identify the likely bottleneck, and explain what simulation, assertions, counters, or measurements would prove the conclusion.

Use the discipline filters together: pair each design choice with a verification plan, then connect architecture behavior to bandwidth, latency, topology, and correctness. GPUDirect RDMA and collective-communication topics are independent exercises, not descriptions of NVIDIA's official interview process.