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  1. Q054Decide when two-flop synchronization is insufficientMediumClock Domain Crossing
  2. Q058Calculate dynamic-power scalingEasyLow-Power Design
  3. Q081Trade speed for leakage with multi-Vt cellsEasyPhysical Design
  4. Q084Scoreboard burst-to-single conversionHardVerification
  5. Q086Recognize LL/SC reservation failureEasyComputer Architecture
  6. Q092Distinguish clock-group relationship typesEasyStatic Timing Analysis
  7. Q103Relieve localized routing congestionEasyPhysical Design
  8. Q138Write a non-pipelined UVM bus driverMediumUVM
  9. Q158Capture a loop variable in fork...join_noneMediumSV
  10. Q220Period after pipelining an OR treeMediumTiming and STA
  11. Q240Apply the UVM factory patternEasyUVM
  12. Q246Choose first-order setup and hold fixesEasyStatic Timing Analysis
  13. Q261Build a LIFO scoreboardEasyVerification
  14. Q267Size and verify an asynchronous FIFOHardClock Domain Crossing
  15. Q268Build a recovery plan from GPU error eventsHardFirmware & Validation
  16. Q285Design and verify a round-robin arbiterHardRTL Design
  17. Q288Design a two-stage pipelined UVM driverHardUVM
  18. Q292Protect a feedthrough across a switchable domainMediumLow-Power Design
  19. Q294Partition a cache addressMediumComputer Architecture
  20. Q310Resolve an immediate pipeline data dependencyEasyComputer Architecture
  21. Q334Match low-power techniques to power componentsEasyLow-Power Design
  22. Q352Constrain one triplicate and seven singletonsMediumSystemVerilog Constraints
  23. Q355Find each scan chain's first failing patternHardDFT & Physical Design
  24. Q360Code an active-low asynchronous-reset registerEasyRTL Design
  25. Q403Reason about nonblocking assignment updatesEasySV
  26. Q417Count ones in seven bitsEasyRTL Design
  27. Q435Choose Mealy timing for an immediate matchEasyRTL Design
  28. Q453Two-to-one weighted arbiterMediumComputer Architecture
  29. Q459Cross a request between powered voltage domainsHardLow-Power Design
  30. Q467Balance a pipeline with one added registerMediumComputer Architecture
  31. Q471Maintain true LRU state for four waysMediumComputer Architecture
  32. Q484Remove false dependencies in Tomasulo schedulingMediumComputer Architecture
  33. Q499Assert set-dominant fault retentionMediumAssertions and Formal
  34. Q517Timestamp exactly 100 rising edgesEasyVerification Utilities
  35. Q532Find fmax for a half-cycle timing pathMediumStatic Timing Analysis
  36. Q584Throttle with temperature hysteresisMediumLow Power Design
  37. Q585Replace UVM types without editing the environmentEasyUVM
  38. Q586XNOR from one 2-to-1 muxEasyRTL Design
  39. Q592Verify a three-byte serializerHardVerification
  40. Q595Constrain five non-overlapping address windowsMediumSystemVerilog Constraints
  41. Q613Build an 8-to-1 mux from 2-to-1 muxesEasyDigital Logic
  42. Q620Use different setup and hold uncertaintyMediumStatic Timing Analysis
  43. Q633Identify the role of a UVM virtual sequenceEasyUVM
  44. Q645Check two synchronized flags for reconvergenceMediumCDC and Reset
  45. Q678Recognize write-back cache behaviorEasyComputer Architecture
  46. Q682Implement a divide-by-four clock modelEasyRTL Design
  47. Q687Pulse on every adjacent pair of onesEasyRTL Design
  48. Q689Detect overlapping 1101 sequencesMediumRTL Design
  49. Q702Explain the routing antenna effectEasyPhysical Design
  50. Q746Verify a synchronous FIFOMediumVerification
  51. Q748Explain CRPR in a timing reportEasyStatic Timing Analysis
  52. Q751Use the Exclusive cache-coherence stateEasyComputer Architecture
  53. Q761Trade ICG granularity for fanout and timingMediumLow-Power Design
  54. Q763Constrain truly unrelated clock domainsEasyStatic Timing Analysis
  55. Q766Implement a parameterized shift registerEasyRTL Design
  56. Q772Convert between binary and Gray codeMediumClock Domain Crossing
  57. Q778Quarantine traffic after peer resetMediumCDC and Reset
  58. Q780Apply clock skew to setup and holdEasyStatic Timing Analysis
  59. Q785Match each signal type to a CDC techniqueEasyClock Domain Crossing
  60. Q795Check per-channel link creditsHardComputer Architecture
  61. Q815Reset state behind a gated clockMediumLow-Power Design
  62. Q854Detect overlapping five-bit palindromesMediumRTL Design
  63. Q858Explain what functional coverage measuresEasyVerification
  64. Q859Compare synchronous and asynchronous resetEasyRTL Design
  65. Q861Share a named UVM configuration eventMediumSystemVerilog and UVM
  66. Q862Design glitch-free clock gatingMediumLow-Power Design
  67. Q864Count coalesced memory segmentsMediumFirmware
  68. Q873Reverse-engineer a sliced shared cacheHardComputer Architecture
  69. Q875Explain parallel VIPT lookup and translationMediumComputer Architecture
  70. Q877Set-dominant sticky fault bitsEasyRTL Design
  71. Q885Order a coherent CPU-to-GPU doorbellMediumComputer Architecture
  72. Q889Track parity history with two state bitsMediumRTL Design
  73. Q896Find the lowest set laneEasyRTL Design
  74. Q906Score lane returns for one tagged operationMediumSystemVerilog and UVM
  75. Q910Constrain mutually exclusive component ownershipMediumSystemVerilog Constraints
  76. Q915Use checked down-casting in SystemVerilogEasySV
  77. Q917Fix event-loss and shared-state monitor bugsMediumVerification
  78. Q918Choose always_comb over a manual sensitivity listEasyRTL Design
  79. Q938Constrain four lane addresses across two segmentsMediumSystemVerilog and UVM
  80. Q951Implement asynchronous FIFO full and empty logicHardClock Domain Crossing
  81. Q970Preserve width through dependent additionsEasyRTL Design
  82. Q974Check an incrementing pulse intervalMediumAssertions
  83. Q987Order the digital ASIC implementation flowEasyASIC Flow
  84. Q990Explain OCV derates and temperatureMediumStatic Timing Analysis
  85. Q1017Identify sources of clock uncertaintyEasyStatic Timing Analysis
  86. Q1040Scale distributed-wire delay with lengthEasyPhysical Design
  87. Q1054Detect the wildcard pattern 110?01HardRTL Design
  88. Q1058Bounded byte-string palindrome checkEasyFirmware & Validation
  89. Q1066Predict opposite-direction crosstalk delayEasyPhysical Design
  90. Q1087Respond to a contained uncorrectable ECC errorMediumPost-Silicon Validation
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