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  1. Q061Place Posted DDR Commands from tRCD, AL, CL, and tRPMediumTiming
  2. Q068UVM monitor for a framed byte streamMediumSystemVerilog & UVM
  3. Q093Cache tag, index, and offset bitsEasyComputer Architecture
  4. Q106Assign UVM run-phase objection ownershipMediumUVM
  5. Q116Local repair for a hold violationEasyTiming and STA
  6. Q121Reason about fork join_none and wait forkEasySV
  7. Q125Distinguish RAM port and read-during-write modesMediumComputer Architecture
  8. Q153Check a cryptographic stream with C-DPIHardFirmware
  9. Q154Code asynchronous reset assertion with two-edge releaseMediumClock and Reset Domains
  10. Q164Separate Pipeline Frequency, Throughput, and LatencyMediumComputer Architecture
  11. Q177Classify CMOS power componentsEasyLow Power
  12. Q193Resolve Read and Write Requests on a Shared PortMediumProtocols and Interfaces
  13. Q226Prove clock-gating entry and wake safetyHardAssertions and Formal
  14. Q228Verify a one-input, three-output packet routerMediumUVM
  15. Q230Order Common Hardware-Description Abstraction LevelsEasyTiming
  16. Q231Add clock enable and operand isolation to an accumulatorMediumTiming
  17. Q235Parse a Fixed DV Log Line with an Anchored RegexEasyDesign Verification
  18. Q238Predict Priority from If and Case StatementsEasyRTL Design
  19. Q242Implement a four-phase CDC event handshakeMediumClock and Reset Domains
  20. Q278Assertions for one outstanding CXL-like requestMediumAssertions and Formal
  21. Q279Choose complete data-path performance metricsMediumDesign Verification
  22. Q280Classify timing-path startpoints and endpointsEasyTiming
  23. Q287Trace Firmware from ELF File to a Halted CoreMediumFirmware
  24. Q336Implement a Three-Tap FIR from Its Transfer FunctionMediumComputer Architecture
  25. Q373Build one Boolean function from NAND gatesEasyRTL Design
  26. Q376Reject Input Glitches Shorter than Four SamplesMediumRTL Design
  27. Q378Balance the Benefits and Costs of Process ScalingEasyPhysical Design
  28. Q380Two-entry skid buffer with flushHardRTL Design
  29. Q394Identify Legal I2C Data and Acknowledge TimingEasyFirmware
  30. Q396Divide a 2 MHz clock by twoEasyRTL Design
  31. Q406Constrain a bounded packet splitMediumSystemVerilog & UVM
  32. Q413Identify the cache with the most conflict pressureEasyComputer Architecture
  33. Q422Order isolation around power-offEasyLow Power
  34. Q424Consume completed Ethernet receive descriptorsMediumFirmware
  35. Q426Evaluate Unary Reduction OperatorsEasySV
  36. Q456Convert DDR Clock Rate into Bus BandwidthEasyTiming
  37. Q466Order self-modifying Hexagon codeHardFirmware
  38. Q482Order a safe voltage-frequency transitionMediumTiming
  39. Q493Two-core MESI reference modelMediumComputer Architecture
  40. Q497Select the oldest ready micro-operationMediumRTL Design
  41. Q505Verify a four-by-four AXI bridgeMediumUVM
  42. Q515Trade a Shared Iterative Unit against Required ThroughputMediumComputer Architecture
  43. Q524Explain Why a CMOS Transmission Gate Uses Two DevicesEasyPhysical Design
  44. Q528Debug a Queue That Advances While StalledMediumMemory Systems
  45. Q546Build a checksummed diagnostic frameMediumFirmware & Validation
  46. Q575Compare TX Emphasis, CTLE, and DFEEasyProtocols and Interfaces
  47. Q580Apply a MESI remote-write transitionMediumComputer Architecture
  48. Q602Prove a register implements twelve data bitsHardUVM
  49. Q616Identify how PCIe generations raise usable bandwidthEasyProtocols and Interfaces
  50. Q626Recognize a safe asynchronous-FIFO pointer schemeMediumClock and Reset Domains
  51. Q630Implement a four-requester round-robin arbiterMediumRTL Design
  52. Q632Convert between Canonical Minterm and Maxterm FormsEasyRTL Design
  53. Q644Choose directed or constrained-random debug stimulusEasyDesign Verification
  54. Q716Verify an AHB-to-APB bridgeMediumUVM
  55. Q728Choose an optimum repeater countMediumTiming
  56. Q729Size a Width-Converting Asynchronous FIFOMediumMemory Systems
  57. Q736One-outstanding-event CDC handshakeMediumCDC and Reset
  58. Q745Predict Hardware from Bounded and Unbounded RTL LoopsMediumTiming
  59. Q753Scoreboard for split responsesMediumSystemVerilog & UVM
  60. Q764Choose a Fixed-Point Format for Range and ResolutionEasyRTL Design
  61. Q773Map Complex Baseband I/Q onto an RF CarrierMediumASIC Fundamentals
  62. Q786Distinguish SystemVerilog Functions and TasksEasyTiming
  63. Q787Match Common Memory Types to Their Storage BehaviorEasyTiming
  64. Q797Gate Functional DDR Commands Around TrainingHardClock and Reset Domains
  65. Q798Constrain Gray-Bus Delay and Skew Without Masking the ChecksHardClock and Reset Domains
  66. Q804Verify predictor rollback after a mispredictionHardComputer Architecture
  67. Q820Preserve Correct State in a Five-Stage PipelineHardComputer Architecture
  68. Q824Formal harness for one coherent cache lineHardAssertions & Formal
  69. Q829Build a Two-Stage Four-by-Four Gate-Level MultiplierHardRTL Design
  70. Q838Identify VCS Build and Simulation ArtifactsEasyUVM
  71. Q867Compare Block-Diagram and RTL-Wrapped DDR IPEasyFPGA Design
  72. Q892Find the first severe entry in a wraparound logMediumPost-Silicon Validation
  73. Q902Calculate UART Baud and Payload RatesEasyProtocols and Interfaces
  74. Q941Choose the deepest allowed idle stateEasyLow Power
  75. Q950Distinguish Mealy and Moore Output BehaviorEasyRTL Design
  76. Q954Select CDC structures for five signal classesMediumDesign Verification
  77. Q956Decode SPI Mode from CPOL and CPHAEasyFirmware
  78. Q975Handle a valid demand-page faultMediumFirmware
  79. Q982Scan-shift testbench modelMediumPhysical Design and DFT
  80. Q993Verify a cache entering retentionHardClock and Reset Domains
  81. Q1042Convert Baud Rate to Bit RateEasyASIC Fundamentals
  82. Q1048Constrain Gray-pointer crossings without masking themHardClock and Reset Domains
  83. Q1051Choose the CXL protocol for device memoryEasyComputer Architecture
  84. Q1056Count unique detected faultsMediumPhysical Design and DFT
  85. Q1080Trace a Transaction Through a UVM EnvironmentEasyUVM
  86. Q1081Find the worst setup pathMediumTiming and STA
  87. Q1085Locate setup and hold windows around a capture edgeEasyTiming
  88. Q1093Bounded MMIO command driverMediumFirmware & Validation
  89. Q1105Why Gray-code an asynchronous FIFO pointerEasyCDC & RDC
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