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Google-Style ASIC Interview Questions
Filtered interview questions
Showing 61 of 61All questions visible
- Q080DesignOrder an RTL-to-GDS flowPhysical design · RTL-to-GDSEasy
- Q129DesignAverage four accepted samplesDesign · SystemVerilogEasy
- Q188ArchControl a link with return creditsArchitecture · InterconnectMedium
- Q236DesignImplement a fair four-requester arbiterDesign · SystemVerilogMediumP
- Q267DesignChoose coupled setup and hold ECOsDesign · STAHardP
- Q314DesignChoose arithmetic shift behaviorDesign · SystemVerilogEasyP
- Q323FWInterpret SECDED memory errorsSilicon · ReliabilityEasyP
- Q336DVRecognize vacuous successDV · Formal verificationEasyP
- Q337DesignRelease reset synchronouslyDesign · RDCEasyP
- Q339DVPlace a formal environment constraintDV · Formal verificationMediumP
- Q365FWBisect a firmware-to-RTL boot hangFW · DebugHardP
- Q386DesignArchitect scan, MBIST, and JTAG accessDesign · DFTHardP
- Q393DesignTransfer a narrow event pulseDesign · CDCEasyP
- Q410DesignSequence isolation and state retentionLow power · Power sequenceMediumP
- Q436DVConstrain a unique aligned queueDV · SystemVerilogEasyP
- Q438DesignSpot an unintended latchDesign · SystemVerilogEasyP
- Q444FWReplace a register bit field safelyFW · Bit manipulationEasyP
- Q452DesignCompute setup and hold slackTiming · STAMediumP
- Q453DesignGenerate a scan shift-capture sequenceDFT · ScanMediumP
- Q537DesignChoose a localized IR-drop repairDesign · Physical designMediumP
- Q542ArchCheck coherent transactions under reorderingArch · Cache coherenceHardP
- Q548DVUse polymorphism through a base handleDV · SystemVerilogEasyP
- Q561DVOrder common UVM phasesDV · UVMEasyP
- Q575DVVerify a wakeup under clock and reset racesDV · Low powerHardP
- Q585DVConnect a sequencer to a driverDV · UVMEasyP
- Q600DV · DesignSize a value with clog2Design · SystemVerilogEasyP
- Q648FWCharacterize a marginal link across PVTSilicon · ReliabilityMediumP
- Q654DesignAvoid multi-bit reconvergence errorsDesign · CDCMediumP
- Q670DVClassify a formal propertyDV · FormalEasyP
- Q686DesignSynchronize a persistent status bitDesign · CDCEasyP
- Q706FWClear a write-one-to-clear interruptFW · MMIOMediumP
- Q725DVBuild a FIFO UVM testbenchDV · UVMMediumP
- Q737FWPoll a device with a bounded timeoutFW · MMIOMediumP
- Q744ArchSplit a cache addressArch · CacheEasyP
- Q759DesignBuild a saturating counterDesign · SystemVerilogMediumP
- Q781ArchSeparate coherence from consistencyArchitecture · Cache coherenceEasyP
- Q783FWLocalize an intermittent HBM lane failureSilicon · HBMHardP
- Q785DesignPlace isolation and retention correctlyLow power · IsolationEasyP
- Q788DesignCalculate maximum clock frequencyDesign · STAEasyP
- Q833DesignScale CMOS dynamic powerDesign · Low powerEasyP
- Q834DVMake a verification-closure caseDV · Verification planningHardP
- Q836DesignConstrain a three-cycle datapathTiming · STAMediumP
- Q848DesignResolve a read-and-clear counter raceDesign · SystemVerilogMediumP
- Q910Design · ArchBuild a two-stage elastic packet pipeDesign · SystemVerilogHardP
- Q913DVSeparate a function from a taskDV · SystemVerilogEasyP
- Q920DVMatch out-of-order responses by IDDV · UVMMediumP
- Q953ArchClassify accelerator bottlenecks from countersArch · Performance countersMediumP
- Q987FWStart first-silicon interface debugSilicon · Bring-upEasyP
- Q992DVAssert ready-valid stability and responseDV · SystemVerilog assertionsMediumP
- Q1003DesignSize an asynchronous FIFO from ratesDesign · CDCMediumP
- Q1011ArchImplement exact four-way LRU stateArchitecture · CacheMediumP
- Q1037FWRead a changing MMIO registerFW · MMIOEasyP
- Q1049DVProve a fair round-robin arbiterDV · Formal verificationHardP
- Q1063DVThrottle forked jobs and protect shared completion stateGoogle · DVHardP
- Q1072DesignCross commands across independent resetsDesign · CDCHardP
- Q1074DesignTrack old values in sequential RTLDesign · SystemVerilogEasyP
- Q1077DesignApply clock skew consistentlyTiming · STAEasyP
- Q1098DesignKnow which violation frequency can fixDesign · STAEasyP
- Q1126ArchCompare true LRU with tree PLRUArchitecture · CacheMediumP
- Q1148ArchFind neighbors in a torus topologyArch · InterconnectEasyP
- Q1155DVSample a ready-valid monitor correctlyDV · UVMMediumP
Study path
Google-style ASIC interview preparation
Practice evidence-driven RTL and architecture across arbitration, cache coherence, CDC, formal assertions, UVM, firmware, power, timing, and post-silicon debug. Begin with the contract and invariants before proposing the implementation.
Finish with a validation strategy that covers corner cases and the metrics or experiments needed to distinguish correctness, timing, and performance failures. These independent exercises do not describe Google's official interview process.