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  1. Q070Choose arithmetic shift behaviorEasyRTL Design
  2. Q083Interpret SECDED memory errorsEasyPost-Silicon Validation
  3. Q094Recognize vacuous successEasyAssertions and Formal
  4. Q096Release reset synchronouslyEasyReset Domain Crossing
  5. Q099Place a formal environment constraintMediumAssertions and Formal
  6. Q128Bisect a firmware-to-RTL boot hangHardFirmware
  7. Q160Architect scan, MBIST, and JTAG accessHardDFT
  8. Q175Transfer a narrow event pulseEasyClock Domain Crossing
  9. Q192Control a link with return creditsMediumComputer Architecture
  10. Q214Sequence isolation and state retentionMediumLow Power
  11. Q251Constrain a unique aligned queueEasySystemVerilog Constraints
  12. Q254Spot an unintended latchEasyRTL Design
  13. Q266Replace a register bit field safelyEasyFirmware
  14. Q272Choose coupled setup and hold ECOsHardTiming and STA
  15. Q276Compute setup and hold slackMediumTiming
  16. Q277Generate a scan shift-capture sequenceMediumDFT
  17. Q319Order an RTL-to-GDS flowEasyPhysical Design
  18. Q391Choose a localized IR-drop repairMediumPhysical Design
  19. Q397Check coherent transactions under reorderingHardComputer Architecture
  20. Q404Use polymorphism through a base handleEasySV
  21. Q419Order common UVM phasesEasyUVM
  22. Q436Verify a wakeup under clock and reset racesHardLow Power Verification
  23. Q448Connect a sequencer to a driverEasyUVM
  24. Q463Size a value with clog2EasySV
  25. Q516Characterize a marginal link across PVTMediumPost-Silicon Validation
  26. Q523Avoid multi-bit reconvergence errorsMediumClock Domain Crossing
  27. Q540Classify a formal propertyEasyAssertions and Formal
  28. Q561Synchronize a persistent status bitEasyClock Domain Crossing
  29. Q582Clear a write-one-to-clear interruptMediumFirmware
  30. Q604Build a FIFO UVM testbenchMediumUVM
  31. Q618Poll a device with a bounded timeoutMediumFirmware
  32. Q625Split a cache addressEasyComputer Architecture
  33. Q638Build a saturating counterMediumRTL Design
  34. Q667Separate coherence from consistencyEasyComputer Architecture
  35. Q669Localize an intermittent HBM lane failureHardPost-Silicon Validation
  36. Q671Place isolation and retention correctlyEasyLow Power
  37. Q674Calculate maximum clock frequencyEasyStatic Timing Analysis
  38. Q731Scale CMOS dynamic powerEasyLow Power Design
  39. Q733Make a verification-closure caseHardDesign Verification
  40. Q735Constrain a three-cycle datapathMediumTiming
  41. Q749Resolve a read-and-clear counter raceMediumRTL Design
  42. Q819Build a two-stage elastic packet pipeHardRTL Design
  43. Q821Separate a function from a taskEasySV
  44. Q828Match out-of-order responses by IDMediumUVM
  45. Q869Classify accelerator bottlenecks from countersMediumComputer Architecture
  46. Q904Start first-silicon interface debugEasyPost-Silicon Validation
  47. Q911Assert ready-valid stability and responseMediumAssertions and Formal
  48. Q924Size an asynchronous FIFO from ratesMediumClock Domain Crossing
  49. Q933Implement exact four-way LRU stateMediumComputer Architecture
  50. Q963Read a changing MMIO registerEasyFirmware
  51. Q978Prove a fair round-robin arbiterHardAssertions and Formal
  52. Q1002Cross commands across independent resetsHardCDC and Reset
  53. Q1004Track old values in sequential RTLEasyRTL Design
  54. Q1008Apply clock skew consistentlyEasyTiming
  55. Q1035Know which violation frequency can fixEasyStatic Timing Analysis
  56. Q1050Average four accepted samplesEasyRTL Design
  57. Q1071Compare true LRU with tree PLRUMediumComputer Architecture
  58. Q1091Implement a fair four-requester arbiterMediumRTL Design
  59. Q1094Find neighbors in a torus topologyEasyComputer Architecture
  60. Q1103Sample a ready-valid monitor correctlyMediumUVM
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