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  1. Q057Out-of-order scoreboard for tagged pixel jobsHardSystemVerilog & UVM
  2. Q073Convert a Turnstile Protocol into an FSMMediumProtocols and Interfaces
  3. Q102Assertions for a one-beat AXI writeMediumAssertions & Formal
  4. Q105Return a checked 32-bit Fibonacci numberEasyFirmware
  5. Q108Analyze Setup and Hold Across 100 and 150 MHz ClocksHardTiming
  6. Q124Release reset safely in two clock domainsEasyCDC & RDC
  7. Q126Use Wildcard Case Constructs without Hiding UnknownsMediumDesign Verification
  8. Q132Build accepted-traffic cross coverageMediumFunctional Coverage
  9. Q134Preserve precise state in an out-of-order coreMediumComputer Architecture
  10. Q135Fair scheduler for two memory banksHardRTL Design
  11. Q141Order the major digital ASIC development stagesEasyRTL Design
  12. Q173Choose RS-232 or RS-485 for a Noisy Multidrop CableEasyProtocols and Interfaces
  13. Q216Explain SerDes Encoding and Transition DensityEasyProtocols and Interfaces
  14. Q223Classify synthesizable and testbench-only constructsEasySV
  15. Q233Preserve Carry with Explicit Expression WidthsMediumSV
  16. Q241Verify RW, RO, reserved, and W1C register fieldsHardDesign Verification
  17. Q248Detect Every Overlapping Run of Three 8'h23 BytesMediumRTL Design
  18. Q255Evaluate four timing checks from event timesMediumTiming
  19. Q270Separate related-clock timing from asynchronous CDCEasyClock and Reset Domains
  20. Q290Place a dense neural-network kernelMediumComputer Architecture
  21. Q297Calculate Best- and Worst-Case Packet LatencyMediumComputer Architecture
  22. Q306UVM monitor for a single-outstanding AXI writeMediumSystemVerilog and UVM
  23. Q307Calculate Schmitt-Trigger HysteresisEasyProtocols and Interfaces
  24. Q338Sequence DDR3 Initialization and PHY TrainingMediumTiming
  25. Q340Compare Conventional RIE with ICP EtchingEasyPhysical Design
  26. Q358Implement a checked SystemVerilog downcastEasyProtocols and Interfaces
  27. Q359Model a four-bit MISR signatureMediumDFT & Physical Design
  28. Q371Implement a Stock-Aware 75-Cent Vending FSMMediumRTL Design
  29. Q381Separate skew, jitter, latency, and uncertaintyEasyTiming
  30. Q388Drive a stalled request with the UVM pull protocolMediumUVM
  31. Q412Sort Signed Integers In Place with Insertion SortEasyFirmware
  32. Q445Compare synchronous and asynchronous FIFO controlEasyClock and Reset Domains
  33. Q454Order a descriptor before an MMIO doorbellMediumFirmware & Validation
  34. Q458Convert a synchronous level into a one-cycle rising pulseEasyRTL Design
  35. Q460Split a set-associative cache addressEasyComputer Architecture
  36. Q486Validate nested parentheses and bracketsEasyFirmware & Validation
  37. Q496Check framed serial even parityMediumRTL Design
  38. Q538UVM checker for register retentionHardLow Power
  39. Q541Derive a Four-Bit Carry-Lookahead AdderHardRTL Design
  40. Q543Compare Tri-State and Open-Drain Shared LinesEasyRTL Design
  41. Q549Pack four display pixels with backpressureMediumRTL Design
  42. Q552Choose a coherent-I/O stale-data litmusMediumComputer Architecture
  43. Q566Determine an NMOS operating regionMediumPhysical Design
  44. Q574Code a parameterized 4-to-1 mux two waysEasyRTL Design
  45. Q589Reconstruct a silicon-only failureMediumDesign Verification
  46. Q598Turn a Workload into an SoC Architecture BudgetMediumLow Power
  47. Q614Build a 256-bit serial collector reference modelMediumDesign Verification
  48. Q634Distinguish AXI-Lite from AXI3EasyDesign Verification
  49. Q637Check NoC credit conservationMediumComputer Architecture
  50. Q688Compute wrapped performance-counter deltasMediumPost-Silicon & Reliability
  51. Q692Draw Static-CMOS Gates and Calculate Inverter Noise MarginsMediumPhysical Design
  52. Q710Implement a coordinated-reset depth-16 asynchronous FIFOHardClock and Reset Domains
  53. Q711Glitch-free gated test clockEasyRTL Design
  54. Q715Token-limited priority arbiterMediumComputer Architecture
  55. Q730Publish a message to an eight-slot mailboxMediumFirmware & Validation
  56. Q737Identify an asynchronous-reset recovery violationEasyClock and Reset Domains
  57. Q740Generate a Divide-by-2.5 Fractional Tick SequenceHardTiming
  58. Q743Derive min and max input/output delay constraintsHardTiming
  59. Q756Plan PCIe endpoint transaction-layer verificationMediumUVM
  60. Q769Choose the center of a passing delay windowEasyTiming & STA
  61. Q783Repair a Negative-Slack Datapath by PipeliningMediumTiming
  62. Q789Transfer Fast Events to a Slow Clock Exactly OnceHardClock and Reset Domains
  63. Q792Recognize and repair a combinational loopEasySV
  64. Q802Separate ISA Guarantees from Core ImplementationMediumFirmware
  65. Q835Constrain aligned transactions inside one pageMediumProtocols and Interfaces
  66. Q856Resolve a Load-Use Dependency in a Five-Stage PipelineMediumComputer Architecture
  67. Q860Cross a burst count with a Gray counterMediumCDC & RDC
  68. Q870Choose an FPGA Configuration ModeEasyFirmware
  69. Q874Match out-of-order AXI read responsesHardUVM
  70. Q887Time Two Related FPGA Clock DomainsMediumTiming
  71. Q890Prove bounded bridge forward progressHardAssertions and Formal
  72. Q903Choose Blocking and Nonblocking Assignments by Process TypeEasyComputer Architecture
  73. Q908Detect Overlapping 1011 SequencesMediumRTL Design
  74. Q912Contain metastability without claiming to eliminate itEasyClock and Reset Domains
  75. Q981Map functions to FPGA resourcesEasyTiming
  76. Q989Choose Logical Equality or Case EqualityEasySV
  77. Q999Sort Three Bytes Serially with One ComparatorHardComputer Architecture
  78. Q1006Pair setup and hold multicycle constraintsMediumTiming & STA
  79. Q1020Remove a Static-1 Hazard from a Two-Level Boolean NetworkMediumRTL Design
  80. Q1047Quiesce before acknowledging power-downMediumLow Power
  81. Q1049Implement Signed Eight-Bit Add/Subtract with OverflowEasyRTL Design
  82. Q1065Size a synchronizer from an MTBF targetMediumClock and Reset Domains
  83. Q1078Write primary, generated, virtual, and asynchronous clock constraintsHardTiming
  84. Q1079Constrain a repeating three-memory address mapEasySystemVerilog & UVM
  85. Q1095Review and scope false-path candidatesMediumClock and Reset Domains
  86. Q1104Build Traceable Verification Items from a SpecificationMediumFunctional Coverage
  87. Q1106Assert stable AXI payload under backpressureMediumAssertions and Formal
  88. Q1108Compute FIFO depth from an exact event scheduleMediumComputer Architecture
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