1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ049

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Q049DVASIC interview problem

APB Protocol Monitor without SVA

TechniquesDVAPBProtocol monitorState machineLatency

DifficultyMedium

TopicProtocol Checking

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Monitor an Advanced Peripheral Bus (APB) transfer at each rising clock edge and detect setup/access sequencing violations without using assertions.

Class declarationSystemVerilog

class ApbMonitor;
  void sample(bit psel, bit penable, bit pready, bit pwrite,
              longint paddr, longint pwdata, int pstrb, bit pslverr);
  int error_count();
endclass

Example input and output

Use this case to check your interpretation

Input

cycle 0: PSEL=1, PENABLE=0, PADDR=0x40
cycle 1: PSEL=1, PENABLE=1, PREADY=0
cycle 2: PSEL=1, PENABLE=1, PREADY=1

Output

one APB transfer completes at cycle 2; address remains 0x40 through the wait state

Explanation

The setup phase precedes the access phase, and all control fields remain stable while PREADY is low.

Requirements (4)

Every access phase must be preceded by a setup phase.
Address, direction, write data, and strobes remain stable while PREADY is low.
PSLVERR is meaningful only on a completing access transfer.
Support legal back-to-back transfers and flag an access that stalls beyond N cycles.