1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ026

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Q026DVASIC interview problem

Four-Phase Request/Acknowledge Monitor

TechniquesDVHandshakeProtocol monitorData stabilityTimeout

DifficultyMedium

TopicProtocol Checking

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Check a four-phase handshake whose legal sequence is request rise, acknowledge rise, request fall, acknowledge fall. Data is launched with request and held until acceptance.

Class declarationSystemVerilog

class ReqAckMonitor #(int DATA_W = 32);
  void sample(bit req, bit ack, bit [DATA_W-1:0] data);
  int completed_count();
  int error_count();
endclass

Example input and output

Use this case to check your interpretation

Input

cycles: (req,ack) = (0,0), (1,0), (1,1), (0,1), (0,0)

Output

one legal four-phase handshake; no error

Explanation

The request rises before acknowledge, then request falls before acknowledge returns low.

Requirements (4)

Reject acknowledge before request and request withdrawal before acknowledge.
Require data stability from request assertion through acknowledge assertion.
Do not allow a new request until both signals have returned low.
Detect a timeout in each non-idle phase without repeatedly counting the same violation.