1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ182

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Q182DesignDVFollow-up to Q292ASIC interview problem

Detect a starving arbiter requester

TechniquesDVDesignFairnessWatchdogStarvation

DifficultyMedium

TopicArbiters

LanguageSystemVerilog

Requirements6 checkpoints

Problem

Add a watchdog that flags any port that remains continuously asserted but ungranted for more than K sampled cycles.

Class declarationSystemVerilog

class StarvationWatchdog #(int N = 8);
  function void sample(int grant_idx, bit [N-1:0] reqs);
  function bit port_starving(int port);
  function bit any_starving();
endclass

Example input and output

Use this case to check your interpretation

Input

K=2; port1 requests without a grant on sampled cycles0,1,2, then wins on cycle3

Output

wait counts=1,2,3 with starvation asserted after cycle2; cycle3 clears count and flag

Explanation

Continuous ungranted assertion increments through cycles with no winner, and an accepted grant resets that port's watchdog state.

Requirements (6)

Maintain a wait count and starvation flag per port.
Increment a port only while it requests and does not receive the accepted grant.
Clear a port's state when it wins or stops requesting.
Set a global alert when any per-port count exceeds K.
Count asserted requesters during cycles in which there is no grant.
Expose both per-port status and the global alert.