1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ098

Q098DVArchFollow-up to Q097ASIC interview problem

Measure ready/valid handshake latency

TechniquesDVArchReady-validLatencyRunning statistics

DifficultyMedium

TopicTemporal Checks

LanguageSystemVerilog

Requirements5 checkpoints

Track minimum, maximum, total, and average latency from the first valid sample of each transfer through its successful ready/valid handshake.

Class declarationSystemVerilog

class HandshakeLatency;
  function void sample(bit valid, bit ready);
  function real average_latency();
endclass

Use this case to check your interpretation

Input

valid rises at cycle 4; ready first overlaps valid at cycle 7

Output

handshake_latency = 3 cycles

Explanation

Latency is measured from the first pending-valid cycle through the accepting edge, without resetting while valid is stalled.

Define a same-cycle valid-and-ready handshake as zero stalled cycles.
Update statistics exactly once per successful transfer.
Initialize minimum latency from the first completed transfer rather than from zero.
Avoid division by zero and return a real-valued average.
Do not add failed or incomplete transfers to the latency statistics.