1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ097

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Q097DVDesignASIC interview problem

Monitor ready/valid without SVA

TechniquesDVDesignReady-validProtocol monitorTimeout

DifficultyMedium

TopicTemporal Checks

LanguageSystemVerilog

Requirements5 checkpoints

Problem

Implement a cycle-sampled ready/valid monitor without SystemVerilog Assertions. Detect when valid drops before a handshake and when a continuously asserted valid waits more than a configured number of cycles for ready.

Class declarationSystemVerilog

class ReadyValidMonitor;
  function new(int stall_threshold);
  function void sample(bit valid, bit ready);
  function int error_count();
endclass

Example input and output

Use this case to check your interpretation

Input

cycle 0: valid=1, ready=0
cycle 1: valid=1, ready=0
cycle 2: valid=1, ready=1

Output

No transfer on cycles 0-1; one transfer on cycle 2; no protocol error.

Explanation

The procedural monitor requires valid to stay asserted during the stall, counts only valid-without-ready cycles toward the timeout, and completes on valid && ready.

Requirements (5)

Treat valid and ready high in the same sample as one completed transfer.
Once a stalled transfer starts, require valid to remain asserted until handshake.
Count only valid-without-ready cycles toward the stall limit.
Report a prolonged stall once per transfer rather than once per subsequent cycle.
Expose the cumulative error count.