1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ074

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Q074DVArchASIC interview problem

Check delayed and reordered memory writes

TechniquesScoreboardMemoryTimeout

DifficultyMedium

TopicReference Models

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Compare authoritative expected memory writes with delayed or reordered DUT writes. Every expected address and data pair must receive one matching DUT write within a bounded number of cycles.

Class declarationSystemVerilog

class MemoryEventualityChecker;
  function void golden_write(longint addr, int data);
  function void dut_write(longint addr, int data);
  function void tick();
  function int error_count();
  function void end_of_test_check();
endclass

Example input and output

Use this case to check your interpretation

Input

expect write (0x100,0xAA) at cycle 0 and (0x200,0xBB) at cycle 1; DUT writes them reversed at cycles 3 and 4

Output

both writes match; no unexpected, expired, or end-of-test entries

Explanation

Matching uses address and data rather than arrival order, while both observed delays remain within the configured bound.

Requirements (4)

Record each expected write with its arrival cycle.
Match a DUT write to one unmatched expectation with the same address and data.
Report unexpected DUT writes, expired expectations, and unmatched end-of-test entries.
Allow matching order to differ from expected-write order.