1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ131

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Q131DVArchFollow-up to Q074ASIC interview problem

Expire memory expectations without full scans

TechniquesScoreboardDeadline queueLazy deletion

DifficultyHard

TopicReference Models

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Replace the full pending-memory scan with a deadline-ordered structure while preserving fast per-address matching.

Address lookup map and deadline-ordered queue sharing transaction objects — Matching marks the shared object, while expiration examines only ordered queue heads and skips matched entries lazily.

Starting declarationSystemVerilog

expected_txn by_addr[longint][$];
expected_txn deadlines[$];

function void golden_write(longint addr, int data);
function void dut_write(longint addr, int data);
function void tick();

Example input and output

Use this case to check your interpretation

Input

expect A due cycle 5 and B due cycle 7; match B at cycle 3; process deadlines at cycle 5 then 7

Output

A expires once at cycle 5; matched B is lazily skipped at cycle 7

Explanation

The deadline queue visits only its expired head objects and the matched marker prevents B from being reported after successful lookup removal.

Requirements (4)

Store the same transaction object in both lookup structures.
Mark a matched object so deadline processing can skip it lazily.
Process only expired objects at the deadline queue head.
Assume expectations enter in nondecreasing cycle order.