1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ120

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Q120DVDesignASIC interview problem

Build a behavioral synchronous FIFO model

TechniquesDVDesignFIFOCircular pointersOccupancy

DifficultyMedium

TopicReference Models

LanguageSystemVerilog

Requirements6 checkpoints

Problem

Implement a bounded behavioral model of a synchronous hardware FIFO that tracks occupancy and read/write pointer movement and reports illegal pushes or pops.

Class declarationSystemVerilog

class FifoModel;
  function new(int depth);
  function bit push();
  function bit pop();
  function bit push_and_pop();
  function int occupancy();
  function bit is_full();
  function bit is_empty();
endclass

Example input and output

Use this case to check your interpretation

Input

DEPTH=2; while empty call push_and_pop(); call push(); call push(); while nonempty call push_and_pop()

Output

empty bypass succeeds with count=0 and both pointers unchanged; two pushes produce count=2/full; final simultaneous operation keeps count=2 and advances both pointers once

Explanation

The behavioral model tracks only occupancy and pointer movement, distinguishing an empty bypass from a simultaneous operation on stored entries.

Requirements (6)

Require a fixed positive depth.
Reject a push on full and a pop on empty.
Track occupancy, write pointer, and read pointer.
Expose full and empty state.
Support one simultaneous push and pop with unchanged occupancy.
Treat simultaneous push and pop on empty as a legal same-cycle bypass with no stored entry or pointer movement.