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Logic · state · cycle-level contracts

RTL Design Engineer Interview Questions

Build from clean combinational and sequential intent into FSMs, datapaths, FIFOs, backpressure, arbitration, memory interfaces, reset behavior, and timing-aware RTL tradeoffs.

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Difficulty
Showing 30 of 30All questions visible
  1. Q007RTL DesignBuild a synchronous FIFO and race-free BFMFIFO · BFMMedium
  2. Q079RTL DesignBuild a reloadable countdown timerCounter · PulseMedium
  3. Q204FSMsDetect overlapping 1011 sequencesSequence detector · Mealy FSMMedium
  4. Q191RTL DesignPipeline a parameterized barrel rotatorBarrel rotator · PipeliningHard
  5. Q004Clock Domain CrossingChoose a safe clock-domain crossing strategyCDC · MetastabilityMedium
  6. Q009Reset DesignSynchronize reset release in each clock domainReset · Async assertEasy
  7. Q014RTL DesignRegister a glitch-free decoded enableDecode · Clock enableEasy
  8. Q020RTL DesignAbsorb ready/valid backpressure with a skid bufferSkid buffer · Ready/validHard
  9. Q200Reliable RTLDetect and recover an upset one-hot FSMOne-hot · SEUMedium
  10. Q162RTL DesignReverse a physical bus at the lane boundaryBit reversal · Packed vectorsEasy
  11. Q168RTL DesignCount active lanes in a predicate maskPopulation count · ReductionEasy
  12. Q090RTL DesignIncrement a four-digit BCD counterBCD · Ready/validMedium
  13. Q218RTL DesignSearch a synchronous calibration ROMBinary search · Synchronous ROMHard
  14. Q006RTL DesignVote across redundant state monitorsMajority voter · Fault toleranceEasy
  15. Q025RTL DesignStably sort records in a local cache-line bufferStable sort · Single-port memoryMedium
  16. Q041RTL DesignControl a tiny exact-LRU associative cacheLRU · Associative lookupMedium
  17. Q085RTL DesignSchedule bank commands with accepted-slot cooldownScheduler · CooldownMedium
  18. Q141RTL DesignDecode Z wildcards without hiding XDesign · SystemVerilogEasy
  19. Q149RTL DesignDiagnose storage from an incomplete always_comb blockDesign · SystemVerilogEasy
  20. Q177RTL DesignImplement a parameterized binary-to-Gray converterDesign · SystemVerilogEasy
  21. Q102RTL DesignCode an asynchronously reset register with enableDesign · SystemVerilogEasy
  22. Q283Combinational RTLBuild a parameterized N-to-1 multiplexerDesign · SystemVerilogMedium
  23. Q905RTL DesignCompare synchronous and asynchronous resetDesign · SystemVerilogEasyP
  24. Q594RTL DesignCombinational versus sequential logicDesign · Combinational RTLEasyP
  25. Q844FSMsWhy an FSM infers a latchDesign · DVEasyP
  26. Q427Sequential RTLSynchronous rising-edge detectorDesign · Edge detectorEasyP
  27. Q226RTL DesignImplement a synchronous FIFO with exact boundary behaviorDesign · DVMedium
  28. Q781RTL DesignCount consecutive zeros with saturationDesign · RTLEasyP
  29. Q581RTL DesignConvert a synchronous level into a one-cycle rising pulseDesign · RTLEasyP
  30. Q725RTL DesignImplement a four-requester round-robin arbiterDesign · ArbitrationMediumP

Coverage map

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The bars count questions in this prepared role path. Team scope and interview emphasis vary by employer.

  • Easy15
  • Medium12
  • Hard3

Related learning

Review the concept, then return to the question.

These are the guides most often linked by questions in this collection.

  1. 01RTL Logic and StateReview combinational logic, sequential state, counters, arithmetic, and finite-state machines.8
  2. 02RTL Synthesis and ProofReview widths, parameterization, memory inference, pipelining, implementation pressure, and proof evidence.8
  3. 03RTL Clock Boundaries and FlowReview reset, clock boundaries, arbitration, ready-valid flow, FIFOs, and backpressure.7
  4. 04Assignments and Procedural IntentReview blocking and nonblocking updates, specialized blocks, case statements, and inferred state.3
  5. 05Clock Domains and ResetReview domain provenance, reset ownership, safe release, recovery, removal, and RDC.2
  6. 06CDC and ClocksReview crossing protocols, metastability risk, Gray pointers, clock relationships, and gating.1
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