CDC, reset, ready-valid, and FIFO boundaries interview reasoning

Question 1

Which CDC structure fits a level, pulse, or multi-bit payload?

Accepted Answer

Use a destination-domain synchronizer for a persistent single-bit level, a toggle or handshake for events, and a stable-data handshake or asynchronous FIFO for coherent multi-bit transfers. Write down the source and destination clock relationship, event rate, latency budget, and whether loss is allowed. A narrow pulse can disappear between destination edges, so pulse width and event spacing are part of the contract. Synchronizing bus bits independently does not preserve a coherent word. Why interviewers ask: Whether you select a structure from signal semantics instead of applying the same synchronizer everywhere. Common trap: Sending an arbitrary pulse or multi-bit bus through independent two-flop chains.

Question 2

What does a two-flop synchronizer solve, and what does it not solve?

Accepted Answer

A two-flop chain reduces the probability that metastability propagates into destination logic for a single-bit level. It does not eliminate metastability or guarantee event capture, bus coherency, ordering, or reset sequencing. Only the first stage should directly sample the asynchronous signal, and implementation tools should recognize the chain. Mean time between failures depends on clock rates, toggle rate, available settling time, and device parameters. Downstream logic consumes the final stage and must tolerate the synchronizer latency. Why interviewers ask: Whether you understand the probabilistic and deliberately narrow role of the synchronizer. Common trap: Calling the output metastability-free or treating two registers as a complete CDC review.

Question 3

How should reset assertion and release cross clock domains?

Accepted Answer

When immediate assertion is required, reset can assert asynchronously, but each receiving clock domain should release through its own synchronizer so local state leaves reset on controlled edges. Reset policy is domain-specific. A fully synchronous reset can be appropriate when the clock is guaranteed and timing is planned. Synchronize release separately in every domain and constrain or identify the synchronizer stages for implementation tools. Verify recovery and removal timing, reset-domain crossings, and partial-reset interactions. Why interviewers ask: Whether you distinguish reset entry, reset release, clock availability, and implementation timing. Common trap: Presenting asynchronous assertion and synchronous deassertion as a universal rule without stating system assumptions.

Question 4

When does a ready-valid transfer occur?

Accepted Answer

A transfer occurs only on an active clock edge where valid and ready are both asserted. Interface state that accounts for that beat, such as its pointer or occupancy update, should follow that accepted-transfer event. The source may assert valid before ready, and the destination may assert ready before valid. Avoid a module-to-module combinational loop from ready to valid and back unless the interface contract explicitly permits and times it. Separate latency from throughput when explaining pipelining or buffering. Why interviewers ask: Whether all state updates share one unambiguous definition of an accepted beat. Common trap: Advancing data when valid is high even though ready is low.

Question 5

What must remain stable while a ready-valid channel is stalled?

Accepted Answer

Once the source presents valid data and the destination is not ready, the source keeps valid asserted and preserves the payload until a later edge accepts that same beat. The hold obligation carries from one sampled cycle into the next. Assertions should compare the current valid and payload with the previous stalled cycle. A skid buffer can break a long ready path while preserving the pending beat. Why interviewers ask: Whether you reason about backpressure as a temporal obligation rather than a same-cycle expression. Common trap: Allowing the payload to change under valid while ready remains low.

Question 6

How should a FIFO handle simultaneous push and pop at full or empty?

Accepted Answer

Define accepted push and pop events first, then derive pointer and occupancy updates from those events. Simultaneous operations can keep occupancy unchanged, but boundary acceptance depends on the chosen interface contract. Count only accepted operations, not raw requests. Specify whether a pop from full creates space for a same-cycle push and whether a push to empty can bypass to the output. Size pointers for wrap and distinguish full from empty with occupancy, an extra wrap bit, or equivalent logic. Why interviewers ask: Whether your state transitions remain correct at the exact full and empty boundaries. Common trap: Updating count with independent if statements whose priority mishandles simultaneous operations.

Cycle	valid	ready	payload	Result at edge
t0	0	1	none	No transfer
t1	1	0	A	Stall begins
t2	1	0	A	Hold obligation
t3	1	1	A	Transfer A

CDC, reset, ready-valid, and FIFO boundaries

Question indexPractice this reading path.

RTL Clock boundariesCDC and reset strategy selection

Match the crossing structure to the signal

Reason it through

Reason it through

Reason it through

RTL Transfers and storageReady-valid, backpressure, and FIFO boundaries

A stall creates a hold obligation

Reason it through

Reason it through

Reason it through

CDC, reset, ready-valid, and FIFO boundaries

Question indexPractice this reading path.

RTL Clock boundariesCDC and reset strategy selection

Match the crossing structure to the signal

Which CDC structure fits a level, pulse, or multi-bit payload?+

Reason it through

What does a two-flop synchronizer solve, and what does it not solve?+

Reason it through

How should reset assertion and release cross clock domains?+

Reason it through

RTL Transfers and storageReady-valid, backpressure, and FIFO boundaries

A stall creates a hold obligation

When does a ready-valid transfer occur?+

Reason it through

What must remain stable while a ready-valid channel is stalled?+

Reason it through

How should a FIFO handle simultaneous push and pop at full or empty?+

Reason it through