Combinational logic, sequential state, and FSMs interview reasoning

Question 1

What distinguishes combinational from sequential hardware?

Accepted Answer

Combinational outputs are functions of current inputs. Sequential hardware contains state that is sampled on a defined event, usually a clock edge, so behavior also depends on history. Combinational paths have no intentional memory and must assign every output on every path. Sequential paths include registers, an explicit sampling edge, and a defined policy for reset, enable, and simultaneous events. Describe the inferred circuit first. Coding constructs are evidence of intent, not the definition of the hardware. Why interviewers ask: Whether you can translate behavioral language into gates, storage, and cycle-level timing. Common trap: Saying that blocking means combinational and nonblocking means sequential without discussing the process and inferred hardware.

Question 2

How does incomplete assignment infer unintended storage?

Accepted Answer

If a procedural combinational block leaves an output unassigned on any reachable path, that output must retain its previous value. Retention requires storage, so synthesis can infer a latch. Give outputs safe defaults before conditional overrides, or cover every branch explicitly. Use lint to find incomplete assignments and review priority when multiple conditions can be true. A default branch should express real behavior. It should not hide an impossible or unsafe state. Why interviewers ask: Whether you understand why a latch appears instead of memorizing a style rule. Common trap: Adding a casual default that suppresses the warning but changes required behavior.

Question 3

Why use blocking assignments for combinational calculations and nonblocking assignments for registers?

Accepted Answer

Blocking assignments make ordered intermediate calculations within one combinational evaluation clear. Nonblocking assignments schedule register updates together so clocked state observes pre-edge values. Use always_comb with complete blocking assignments for next-value calculations. Use always_ff with nonblocking assignments for state that updates on the same edge. Keep the ownership of each variable unambiguous and avoid mixing styles inside one state-update process. Why interviewers ask: Whether your simulation model matches concurrent hardware behavior at a clock edge. Common trap: Treating the assignment operator alone as proof that a block is combinational or sequential.

Question 4

How should an RTL finite-state machine be structured?

Accepted Answer

Register the current state in a clocked process, compute next state with complete combinational defaults, and define outputs from state or from state plus inputs according to the timing contract. Name states after observable phases of the protocol, not after code locations. State which edge samples every transition condition and what happens when several conditions arrive together. Use assertions for legal transitions, one-hot integrity when applicable, and required progress. Why interviewers ask: Whether the implementation follows a precise temporal contract rather than an ad hoc case statement. Common trap: Leaving next state unassigned, omitting event priority, or assuming reset alone handles every illegal encoding.

Question 5

When should an output be Moore-style or Mealy-style?

Accepted Answer

A Moore-style output depends on registered state, so its logical value follows state updates, although a combinational decode can still glitch. A Mealy-style output also depends on current inputs, which can reduce response latency but adds an input-to-output path. Choose from the interface timing requirement, not from a blanket preference. If a Mealy output crosses a module boundary, account for glitches, timing depth, and input stability. Register an output when downstream logic needs a clean cycle boundary and the added latency is acceptable; state-only decoding is not itself a glitch guarantee. Why interviewers ask: Whether you can trade latency against timing, glitch exposure, and interface clarity. Common trap: Claiming that one style is universally smaller, faster, or safer.

Question 6

How should encoding and illegal-state recovery be chosen?

Accepted Answer

Choose binary, one-hot, Gray, or another encoding from area, decode depth, transition behavior, implementation guidance, and safety goals. Define recovery only to the level the system actually requires. One-hot often simplifies decode at the cost of more state bits, but synthesis results and target technology matter. Illegal-state detection can recover, flag, reset, or fail safe depending on the system contract. Recovery logic needs verification. It should not create an untested transition that hides corruption. Why interviewers ask: Whether you connect encoding to physical implementation and fault behavior. Common trap: Saying one-hot is always fastest or forcing every illegal state directly to idle without considering safety.

Decision	Combinational	Sequential
Depends on	Current inputs	Current inputs and stored state
Typical process	`always_comb`	`always_ff`
Classic failure	Incomplete assignment infers a latch	Ambiguous priority or unsafe reset release

Combinational logic, sequential state, and FSMs

Question indexPractice this reading path.

RTL Logic modelsCombinational and sequential intent

Where the design remembers state

Current inputs determine the result

A clock edge advances state

Reason it through

Reason it through

Reason it through

RTL State and controlFinite-state machines as timing contracts

Join each transition to its sampling edge

Reason it through

Reason it through

Reason it through

Combinational logic, sequential state, and FSMs

Question indexPractice this reading path.

RTL Logic modelsCombinational and sequential intent

Where the design remembers state

What distinguishes combinational from sequential hardware?+

Reason it through

How does incomplete assignment infer unintended storage?+

Reason it through

Why use blocking assignments for combinational calculations and nonblocking assignments for registers?+

Reason it through

RTL State and controlFinite-state machines as timing contracts

Join each transition to its sampling edge

How should an RTL finite-state machine be structured?+

Reason it through

When should an output be Moore-style or Mealy-style?+

Reason it through

How should encoding and illegal-state recovery be chosen?+

Reason it through