1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ032

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Q032ArchDVASIC interview problem

Verify a dictionary-order permutation streamer

TechniquesDVPermutationReady/valid

DifficultyMedium

TopicStreaming Algorithms

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Verify a single-request block that accepts one to seven distinct bytes and streams every permutation in lexicographic order while requests and responses may stall independently.

Permutation streamer accepting one request and holding each unique permutation until the consumer is ready — A request is accepted once, and every emitted permutation remains stable across output stalls.

Interface declarationSystemVerilog

interface perm_if #(int N=7)(input logic clk);
  logic rst_n, req_valid, req_ready;
  logic [3:0] count;
  logic [7:0] item[N];
  logic out_valid, out_ready, out_last, out_error;
  logic [7:0] permutation[N];
  logic [3:0] out_count;
endinterface

Example input and output

Use this case to check your interpretation

Input

accepted distinct bytes=[b,a,c]

Output

[abc, acb, bac, bca, cab, cba]

Explanation

Sorting the captured frame establishes the first lexicographic permutation; successive next-permutation steps produce all 3! results.

Requirements (4)

For a legal count, deep-copy and sort the accepted bytes, then expect exactly count-factorial permutations with unused lanes zero.
A duplicate byte or count outside 1 through 7 produces one final zero-payload error beat and no successful permutations.
Keep req_ready low until the final response handshake; bound the first beat, inter-beat gaps, and total completion when out_ready is high.
Require stable stalled output, out_last only on the final item, and complete cancellation on reset.