1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ119

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Q119DVFollow-up to Q117ASIC interview problem

Exclude illegal coverage combinations

TechniquesDVIllegal binsExclusion setCoverage accounting

DifficultyMedium

TopicFunctional Coverage

LanguageSystemVerilog

Requirements5 checkpoints

Problem

Some type-priority pairs are illegal and must not count toward observed coverage or the expected total. Add an idempotent API for excluding those pairs.

Function headerSystemVerilog

function new(int num_types, int num_prios);
function void add_ignore(int type_id, int priority);
function void sample(packet_t p);
function bit all_combinations_hit();
function real coverage_percent();

Example input and output

Use this case to check your interpretation

Input

2x2 type-priority domain; sample (1,1); add_ignore(1,1) twice; sample the other three legal pairs

Output

legal expected pairs=3; observed legal pairs=3; coverage=100%

Explanation

Exclusion removes a previously observed pair from both numerator and denominator exactly once; duplicate exclusion is idempotent.

Requirements (5)

Validate an excluded pair before registering it.
Registering the same pair twice must not change the expected count twice.
Ignore excluded pairs during sampling.
Handle a pair that was sampled before it was excluded.
Use only non-ignored hits and legal expected pairs for completion and percentage calculations.