1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ091

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Q091ArchDVASIC interview problem

MSI Cache-Coherence Directory Scoreboard

TechniquesDVArchCache coherenceMSITransient states

DifficultyHard

TopicCoherence

LanguageSystemVerilog

Requirements5 checkpoints

Problem

Track a sparse cache directory using the Modified, Shared, Invalid (MSI) protocol. Requests, snoops, invalidation acknowledgements, evictions, and data responses may appear on different interfaces.

Message-signaled-interrupt directory requests and reordered responses matched by identity — The scoreboard tracks directory state and compares each response against the corresponding accepted request.

Type declarationSystemVerilog

typedef enum {CPU_READ, CPU_WRITE, SNOOP_INV, INV_ACK,
              DATA_RSP, EVICT} coh_event_e;

class MsiDirectory #(int AGENTS = 8);
  void observe(coh_event_e event, int agent, longint line_addr,
               int txn_id, int data_version);
  int error_count();
endclass

Example input and output

Use this case to check your interpretation

Input

line X initially I/I
core0 Read X
core1 Read X
core0 Write X

Output

directory states: S/I -> S/S -> M/I, with an invalidation sent to core1 before core0 writes

Explanation

The scoreboard tracks sharers and enforces the single-writer invariant during the S-to-M transition.

Requirements (5)

At most one agent may own a line in Modified state.
Modified ownership implies that no other agent remains a Shared holder.
Represent transient states while invalidations or data transfers are outstanding.
Count required acknowledgements and reject duplicate, stale, or unexpected responses.
Track a data version so the next reader receives the most recent completed write.