▤DescriptionQ815Page ↗UnlockQ815DesignPPremiumNVIDIAASIC interview problemReset state behind a gated clockTechniquesDesignResetClock gatingICGDifficultyMediumTopicLow-Power DesignLanguageSystemVerilogRequirementsLocked◇PremiumUnlock this questionPremium prompts and solutions require a Premium access code.Access codeUnlock question