From I²C sensors to Ethernet networks: explore nine interfaces, their connections, and the transactions firmware sees.
Start with the connection you need
A processor needs to configure sensors, read storage, join a network, and program or test hardware. Each interface defines how to choose a destination, time the bits, and share the connection.
Peripherals and storage
MCU↔Peripheral
I²C and SPI connect sensors; UART carries a byte stream; SD / SDIO serves storage or I/O functions.
During development
Probe↔Chip
JTAG scans test registers; SWD provides an Arm debug connection.
Between systems
Device↔Network / host
USB connects to a host; Ethernet joins a network; CAN shares control messages across a bus.
Interface overview
Select an interface to explore its wiring and a step-by-step transfer.
Use I²C when several peripherals need to share a few controller pins. An address selects a sensor or memory on the same clock and data pair. This saves select pins, but address compatibility and the electrical load still need checking.
One shared bus; the address chooses the device.
01 · Connection
Wiring
Shared clock and data
The controller, sensor at address 0x48 and memory at address 0x50 each connect to SCL, SDA and common ground. SCL and SDA each have a separate pull-up resistor to VDD. Every device can pull a line low or release it.
All three devices share SCL for timing and SDA for addresses and data. An open-drain output can pull a line LOW or release it; the pull-up then restores HIGH so another device can safely take its turn.
Dots mark connections; curved crossings keep SCL, SDA and ground electrically separate.
02 · Transfer
I²C transfer
Choose an address. Step through the write and its acknowledgments.
STARTSDA ↓ while SCL = 1
SCLSDA
START: SDA falls while SCL stays high.
Step 1 of 6
Timing and model details
One controller; ready targets at 0x48 and 0x50; 0x2A accepted as a single data byte. 18 clock pulses in this attempt. START and STOP are line conditions. Address and data windows each show eight bits followed by acknowledgment. For data bits, SDA changes only while SCL is low. Timing is idealized; rise time, setup/hold, arbitration and stretching are not simulated.
Why this step mattersStep 1 of 6, START. START makes every target listen for the next address.
Step 1 of 6
Implementation notes
These calls describe controller operations, not a specific driver API. Firmware normally configures a peripheral and checks its status. The teaching targets accept one byte directly; real devices may need command or register bytes. Bound waits for bus availability and completion. DATA_NACK is shown as a defensive branch; the two responding fixtures always accept 0x2A.
What to watch for
Common mistakes
Shifting the address twice
Check whether the driver expects the 7-bit address or a prepared address byte.
Guessing the pull-up value
Check rise time, bus capacitance, and the pin’s low-level current limit.
Treating every NACK as a wiring fault
Check the address, target readiness, and whether a read is intentionally ending.
Check on the bench
Capture START, address, receiver ACK, payload, and STOP. Then test a missing target and a bounded wait for stretched SCL. Check analog rise time as well as the decoded bytes.
Further details and primary sources +
Release means high
Open-drain outputs pull low or release; pull-ups create high. During a data bit, SDA stays stable while SCL is high. With SCL high, SDA falling marks START and SDA rising marks STOP.
The receiver owns ACK
Eight bits travel most-significant first. On clock nine the transmitter releases SDA; the receiver pulls it low for ACK. A high level is NACK. For a read, the controller receives data and NACKs its final byte before STOP.
Keep ownership through a repeated START
A repeated START begins another address phase without freeing the bus, often after selecting a register to read. Clock stretching extends a low clock period. Multiple controllers require arbitration; this lab uses only one.
Example scope
Conventional open-drain, 7-bit I²C teaching model. Addresses and payload are fixtures, not real device commands. Register formats and recovery procedures belong to each device manual; high-speed and Ultra Fast-mode variations are outside this lab.
Use SPI for a direct exchange with a selected peripheral, such as a display, converter, or memory. The controller provides the clock while separate data wires carry both directions. Check the peripheral’s clock mode and command framing; adding devices usually adds select pins.
Two data paths, timed by one shared clock.
01 · Connection
Wiring
Clocked, both directions
Four separate signals connect controller and peripheral. SCLK supplies the clock, CS_n selects when low, MOSI sends controller data, and MISO carries the peripheral reply. Ground is a separate connection.
The controller generates SCLK and selects the peripheral with CS_n. Separate MOSI and MISO wires carry outgoing and returning bits during the same clock cycles; the peripheral’s command format determines what those bits mean.
SCLK, chip select and MOSI go to the peripheral; MISO returns data while all devices share ground.
02 · Transfer
SPI timing
Select a device, exchange eight bits, then release it. Change the mode or skip selection to compare.
CPOL 0 · idle lowCPHA 0 · sample risingCS_n LOW
MSB →b7b6b5b4b3b2b1b0
MOSI0xA510100101
MISO0x3C00111100
Configure and selectClock held at its idle level
CS_nSCLKMOSIMISO
Clock configured to mode 0; CS_n is LOW. The first bit must already be valid before the first leading edge.
Step 1 of 10
Timing and model details
Eight-bit, MSB-first fixture. The selected, mode-matched peripheral returns 0x3C while the controller sends 0xA5. The fault deliberately leaves CS_n high and assumes the peripheral releases MISO; external bias may affect the measured voltage, so no received byte is predicted. The two-cycle inset follows the selected bit. In CPHA=1 modes, gray dashes precede the first data launch. Edges are schematic; actual data settles after launch and must meet setup/hold limits.
CPOL sets idle LOW (0) or HIGH (1). CPHA selects leading-edge sampling (0) or trailing-edge sampling (1). Amber marks the sample edge.
Mode 0CPOL 0 · CPHA 0↑ Rising edge
Mode 1CPOL 0 · CPHA 1↓ Falling edge
Mode 2CPOL 1 · CPHA 0↓ Falling edge
Mode 3CPOL 1 · CPHA 1↑ Rising edge
The leading edge leaves idle; the trailing edge returns to idle. Match both settings to the peripheral. Mode 0 needs the first bit valid before the first rising edge.
04 · Choose the interface
A shared clock or agreed bit time?
SPIControllerSCLK edges →Peripheral
UARTLocal clockTX → RXLocal clock
SPI supplies the sampling clock, which suits clocked peripherals such as converters and memories. UART reconstructs timing from a start bit and the agreed baud rate.
Choose the interface the device supports. SPI’s command format and chip-select boundaries still come from its data sheet.
Why this step mattersStep 1 of 10, Configure and select. Mode 0 sets idle clock polarity and the sampling edge before CS_n goes LOW.
Step 1 of 10
Implementation notes
The loop expands what an SPI controller does; firmware usually submits a buffer. Mode 0 samples on rising edges. The first bit must already be valid before the first leading edge. A deselected target is modeled as high impedance, not a fixed 0xFF reply. Real pull resistors and device rules determine the line level. Interpret received bytes using the peripheral’s command and status format.
What to watch for
Common mistakes
Matching speed but missing the mode
Both ends must agree on clock polarity and the sampling edge.
Releasing chip select too early
Keep it asserted for the command boundary required by the device.
Expecting an immediate reply
The simultaneous incoming byte may be a prepared value or belong to an earlier command.
Check on the bench
Decode both directions using the selected mode. Check the first bit, all eight sample edges, chip-select setup/hold, and MISO release before selecting another device.
Further details and primary sources +
Polarity names the idle level
Clock polarity, CPOL, sets SCLK idle low or high. The leading edge leaves idle; the trailing edge returns to it. These names still work when a rising edge becomes a falling edge.
Phase names the sample edge
Clock phase, CPHA, selects leading-edge sampling when zero and trailing-edge sampling when one. Modes 0/1 idle low; modes 2/3 idle high. Mode 0 needs the first data bit ready before the first rising edge.
The device defines the message
Read the peripheral contract for bit order, word length, chip-select timing, command fields, and dummy clocks. SPI itself supplies no universal address or acknowledgment byte. An unselected device must release a shared MISO line as specified.
Example scope
Conventional four-wire, active-low-select SPI; eight-bit, most-significant-first examples. Three-wire, daisy-chain, dual/quad data, and device-specific protocols need their own timing rules. There is no single safe clock rate for every SPI device.
Use UART when two devices need a simple byte stream without a clock wire, such as a console or module command link. Start and stop bits give each receiver a timing reference. Both ends must agree on framing and baud rate, and software must define complete messages.
A direct byte link; each end keeps its own time.
01 · Connection
Wiring
TX connects to RX
Device A TX connects to Device B RX. Device B TX connects to Device A RX. The devices share ground but each uses its own clock; there is no clock wire.
Connect each TX output to the other device’s RX input. With no shared clock wire, both ends must agree on the baud rate and frame format; each receiver uses its own clock to sample incoming bits.
Match the baud rate and connect compatible logic-level pins; RS-232 and RS-485 require transceivers.
02 · Transfer
UART frame
8N1: one start bit, eight data bits, one stop bit. Data travels b0 first.
0x53 · 10 bit times · idle high before START and after STOP
Bit time 8.68 µsFrame 86.81 µsPayload ceiling 11,520 B/s
Start = 0. The falling start edge establishes the receiver’s sampling schedule.
Step 1 of 10
Timing and model details
Logic-level UART; 8 data bits, no parity, 1 stop bit. Bit time = 1 / baud; frame time = 10 / baud. Amber markers are ideal sample centers, not a specific receiver oversampling implementation. A high stop bit does not prove the payload is correct. Payload ceiling assumes back-to-back frames with no flow-control pauses. Narrow screens split the same continuous frame into consecutive windows.
One frame takes about 86.8 µs. Idle gaps and application headers reduce useful throughput; baud is not bytes per second.
04 · Choose the interface
A USB console may contain a bridge
ComputerUSB host
USB ↔
BridgeUSB ↔ UART
TX / RX ↔
MCUUART pins
The active bridge buffers and translates between USB packets and UART bytes. A USB connector and logic-level TX/RX are different electrical and protocol interfaces.
UART is useful for logs and module commands. Software must add any message boundaries, checksums, or acknowledgments it needs.
Transmitter drives TX; receiver only samples its RX input
Sent so far
LOW start bit
Response so far
Start detected; data register not complete
Receiving data
Why this step mattersStep 1 of 10, Detect START. The falling start edge gives the receiver a reference for its own sampling clock.
Step 1 of 10
Implementation notes
This is a conceptual hardware receiver, not a software timing loop. Firmware configures baud rate and 8N1, then reads received data with its framing and overrun status. The bad-stop fixture forces the final sample LOW; it does not simulate a particular baud mismatch. Define a policy to discard, flag, and resynchronize after errors. UART framing provides no acknowledgment or end-to-end checksum.
What to watch for
Common mistakes
Connecting TX to TX
Each transmitter connects to the other device’s receiver.
Confusing logic levels with RS-232
Use a suitable transceiver; the electrical signals differ. RS-485 also needs its own transceiver.
Trusting the stop bit as a checksum
A correctly framed 8N1 byte can still contain wrong data.
Check on the bench
Measure a bit interval, decode the known byte, and inspect the stop sample. Exercise back-to-back traffic and receive-buffer overrun; include clock tolerance and interrupt-service latency in the design.
Further details and primary sources +
A falling edge starts the frame
For this non-inverted UART, idle is high and the start bit is low. The receiver detects the start, then uses its local clock to sample near each bit center. Clock error accumulates across the frame.
8N1 describes the framing
Eight data bits travel least-significant first, followed by no parity bit and one high stop bit. The ends must agree on baud rate, data length, parity, and stop configuration. Other UART frame formats exist.
Separate bytes from messages
A framing error means the expected stop level was missing; overrun means receive storage could not keep up. An application still needs message boundaries, validation, and flow control if its sender can outrun the receiver.
Example scope
Logic-level, non-inverted 8N1 UART. The selectable rates are teaching inputs, not guaranteed operating points. Voltage compatibility, oversampling, error tolerance, and optional RTS/CTS hardware flow control are target-specific.
Use JTAG to inspect a chain of devices or test board connections that are difficult to probe. Shared clock and control signals move data through each device’s selected register. The instruction determines what is scanned, so chain order and register lengths are part of the setup.
Bits pass through one chip, then the next.
01 · Connection
Wiring
Parallel control, serial data
The debugger has separate TCK and TMS outputs, each connected in parallel to Device A and Device B. Curved crossings are not junctions. Data out enters A TDI, passes through A selected register and TDO, then B TDI, selected register and TDO, and returns to debugger data in.
The blue TCK and TMS branches deliver the same clock and state-control signal to both chips. The amber serial chain instead passes through each chip’s selected register before returning to the debugger.
TCK and TMS go to both chips; selected registers form the serial chain, with common ground and optional reset omitted.
02 · Transfer
JTAG scan
Capture, shift six bits through the chain, then update the output latches.
1 · Capture2 · Shift 0/63 · Update
TDI input 1 1 0 1 0 0First bit firstNext 1
Device ATDI → selected register → TDO
101
→
Device BTDI → selected register → TDO
011
Observed TDO No bits shiftedOutput latches · A / B 000 / 000
Captured A=101 and B=011. Output latches remain unchanged.
Step 1 of 8
Timing and model details
Two fictional three-bit data registers; captured cells 101011; serial input 110100. Cells are drawn from TDI on the left to TDO on the right. Capture and shift leave separate output latches unchanged. Intermediate TAP states and instruction loading are omitted, so the conceptual Capture and Update buttons do not represent single-clock transitions. Not every JTAG data register drives physical pins.
Why this step mattersStep 1 of 8, Capture. Capture loads the scan cells while the separate output latches keep their previous values.
Step 1 of 8
Implementation notes
The debugger must navigate the TAP states and select the correct instruction before these conceptual operations. This model has two three-bit data registers and an independent output latch. The short-scan case deliberately updates after five clocks; JTAG does not automatically report that length mistake. The comparison is a teaching check against the intended result, not a built-in protocol ACK.
What to watch for
Common mistakes
Chaining the control wires
TCK and TMS reach the targets in parallel; TDI/TDO form the serial path.
Forgetting BYPASS bits
Every device placed in BYPASS still contributes one bit. Count the selected data registers, not the instruction-register lengths.
Reading newly sent bits first
The captured chain contents leave before the replacement bits reach the output.
Check on the bench
Establish a known TAP state, confirm device order and documented register lengths, then compare the captured output with the expected serial sequence. A scan match alone does not prove a device-specific debug operation completed.
Further details and primary sources +
Select the register first
An instruction-register scan chooses which data register each target places between TDI and TDO. The same wires can expose boundary-scan cells, identification, a one-bit BYPASS register, or a device-specific debug register.
Capture, shift, then update
Capture loads a snapshot. Shift clocks old bits out while new bits move in. Update applies the scanned value where that register supports an update. Intermediate TAP states connect these stages; they are not three adjacent states.
Count every selected register
The scan length is the sum of all selected register lengths. BYPASS leaves a one-bit path through an otherwise uninteresting target; it does not remove that device electrically. Boundary Scan Description Language (BSDL) files document the relevant device structure.
Example scope
A selected data-register scan, not a complete TAP or processor debugger. The lab’s registers have explicit capture and update storage. Actual instructions define whether an update changes pins, internal state, or nothing.
Use SWD to program or inspect an Arm target with a small debug connection. The debugger supplies the clock, while request and response phases take turns on one data wire. A valid wire transaction is only one step: access-port reads can return an earlier result.
One data wire; the probe and chip take turns.
01 · Connection
Wiring
One data wire, shared in turns
A debug probe sends SWCLK to the chip debug port. A separate bidirectional SWDIO connection carries request, acknowledgment and data, with only one driver at a time. The probe and target also share ground.
The probe supplies SWCLK, while requests and replies share SWDIO. A turnaround gives the current sender time to release that wire before the other side drives it, avoiding two outputs fighting each other.
SWCLK comes from the probe; neither side drives SWDIO during a turnaround.
02 · Transfer
SWD ownership
Only one side drives SWDIO. Turnaround transfers ownership.
Host = debuggerTarget = debug port
HostTarget
Req8
TA1
ACK3
Data32
P1
TA1
Field lengths in clocks · Req = request · TA = turnaround · P = parity
Read request · 8 clocks. The debugger selects a DP register and the read/write direction.
Step 1 of 6
Timing and model details
46 clocks across shown fields; idle cycles excluded. Field widths are schematic, not proportional to duration. Default one-clock turnaround; ORUNDETECT=0. Read cases select DP RDBUFF; the write selects DP SELECT. WAIT assumes an earlier AP access remains pending; that preceding access sequence is omitted. The target keeps ownership from OK through data and parity during a successful read. SWCLK need not run continuously while idle.
Beyond the wire transfer, ADIv5 Access Port reads are posted. Keep the requested address separate from the result returned now.
RequestReturned result
AP read A→Older value · ignore
AP read B→Value at A
DP RDBUFF→Value at B
RDBUFF collects the final result without starting another AP access. This separate, simplified sequence assumes the same selected AP, successful accesses, and no intervening SELECT or bank changes. Follow the target’s WAIT and error rules.
04 · Choose the interface
When SWD is the smaller connection
JTAG · 4 main signals
TCKTMSTDITDO
SWD · 2 main signals
SWCLKSWDIO
JTAG supports scan chains and boundary-scan testing. SWD provides an Arm debug connection with fewer main signal pins.
Check the chip and probe for supported ports. Neither a pin count nor a connector guarantees the target exposes the debug or test feature you need.
Ground is required. Reset, trace, and other optional signals are excluded from these counts.
Why this step mattersStep 1 of 6, Read request. The request selects a debug-port register and tells the target whether this attempt reads or writes.
Step 1 of 6
Implementation notes
These are probe-level operations, not application CPU loads. Read selects DP RDBUFF after an earlier AP access; write selects DP SELECT. The example uses one-clock turnaround, overrun detection disabled, and valid data parity. WAIT needs bounded retry or deferral. A real driver must also handle FAULT, parity errors, and sticky status using the selected debug-port specification.
What to watch for
Common mistakes
Driving through turnaround
Release SWDIO before the other side takes ownership.
Reading WAIT as zero data
Retry with a bound; WAIT did not return a successful data word.
Ignoring the overrun setting
This lab omits WAIT/FAULT data phases only because ORUNDETECT is disabled.
Check on the bench
Trace the driver for every phase, verify request/data parity, then exercise OK and WAIT separately. For a memory read, also track AP selection, posted results, and error recovery.
Further details and primary sources +
Hand off before answering
The debugger sends the request, then releases SWDIO. After turnaround, the target returns OK, WAIT, or FAULT. On an OK write, another turnaround hands the wire back before the debugger sends data and parity.
WAIT is not data
With overrun detection disabled, WAIT has no data phase. Retry with a bound; inspect and clear the documented error state for FAULT. Turnaround defaults to one clock, but debugger and target settings must agree.
A wire read is not always the requested result
ADIv5 AP reads are posted: a later AP read returns the previous result, and DP RDBUFF retrieves the final one. Validate even parity and follow the access-port completion rules before interpreting a word as fresh memory data.
Example scope
ADIv5 wire-level examples with one-clock turnaround and ORUNDETECT disabled. Initialization, multidrop selection, power-up, and full error recovery are outside this lab; AP posting is explained but not simulated. SWCLK need not run continuously while idle.
Use USB when a device must connect through a computer’s host stack. Descriptors describe its functions and endpoints, and the host schedules transfers. This adds discovery and software setup, but provides a standard connection beyond a board-level byte link. These examples use USB 2.0 full-speed bulk.
The host schedules each packet exchange.
01 · Connection
Wiring
USB 2.0 full-speed connection
The host PHY and device PHY are connected by two continuous wires, D+ and D−, forming one differential data pair used in either direction. VBUS supplies power from the host to the device body outside the PHY. Ground connects the bodies separately and has no direction.
Each PHY converts packet bits to electrical signaling on D+ and D−, one differential data pair. Host and device take turns transmitting on that same pair; VBUS supplies power through a separate connection.
The PHY is the electrical interface; VBUS and ground connect separately from the continuous D+ / D− pair.
02 · Transfer
USB transaction
Time flows down. The host starts both IN and OUT transactions.
HostTime ↓Device
Host sends IN. The payload will travel device → host.
Step 1 of 3
Timing and model details
USB 2.0 full-speed bulk; 12 Mbit/s is raw signaling, not payload throughput. D+ and D− form one shared differential pair. The fixture begins with DATA0 expected. Packet encoding, error retries, enumeration and setup traffic are omitted. NAK does not advance the data toggle. Low-speed USB has no bulk transfers. Packet spacing is not a duration scale.
Why this step mattersStep 1 of 3, IN token. The host schedules IN; the token selects both the device and its endpoint.
Step 1 of 3
Implementation notes
This pseudocode expands host-controller packet handling; application firmware normally submits a USB transfer to a stack. The device is already configured, the expected PID starts at DATA0, and CRC is valid. The receiver advances its expectation when it accepts the expected DATA; the transmitter advances only after receiving ACK. NAK is temporary backpressure, not a hard failure. Bound the overall request by a deadline or cancellation policy. Real stacks also handle STALL, timeouts, retry rules, and duplicate data packets.
What to watch for
Common mistakes
Reversing IN and OUT
Both names use the host’s perspective: IN brings payload to the host.
Treating NAK as permanent failure
The endpoint may be temporarily unready; the host can request again.
Applying bulk rules to every endpoint
Other transfer types have different timing and handshake rules. Low-speed USB does not support bulk.
Check on the bench
Check enumeration, endpoint type, token direction, payload, and handshake. Test NAK followed by a later retry, and a lost ACK without duplicate application delivery. Electrical compliance needs PHY-level measurements too.
Further details and primary sources +
Enumerate before transferring
The host discovers and configures a device using control transfers and descriptors. Endpoints then provide defined data paths. An address identifies the device; endpoint number and direction identify the destination within it.
Follow token, data, handshake
For bulk OUT, the host sends both the OUT token and data; the device acknowledges accepted data. For bulk IN, a device with nothing ready may return NAK instead of data. There is no ACK after that NAK.
Retry without delivering twice
DATA0/DATA1 toggles help the receiver recognize a repeated packet after a lost acknowledgment. Successful progress advances the sequence; NAK does not. Bulk provides retry-based delivery without a guaranteed bandwidth or completion deadline.
Example scope
USB 2.0 full-speed bulk after configuration. Packet fields, CRC, encoding, bit stuffing, hub timing, and electrical compliance are not simulated. USB-C describes connector/power capabilities, not the bulk transaction drawn here; USB 3.x uses additional signaling.
Use Ethernet when a board needs to communicate with computers or other devices across a wired network. Unlike SPI's selected peripheral or USB's host-scheduled transfers, switched Ethernet gives each device a separate link. Start with the MAC, PHY, and one frame before adding IP addresses, sockets, or TCP.
Each board takes its own link to the switch.
01 · Connection
The board bus ends at the PHY
RMII is the digital connection between the MAC and PHY. The 100BASE-TX cable carries a different electrical signal.
MCUCPU · DMA · MAC
PHYCable transceiver
TXD[1:0] TX_EN→Bits + transmit enable
RXD[1:0] CRS_DV←Bits + carrier/data valid
50 MHz REF_CLKCommon timing reference for both blocks
MDC / MDIOPHY configuration + link status
PHY↔Magnetics↔Switch port
Cable: two twisted pairs. One direction per pair in this full-duplex example. Power, reset, and the optional RMII RX_ER signal are omitted.
MAC means Media Access Control: it handles frame fields and checks. The PHY, or physical-layer transceiver, turns the digital stream into cable signaling and recovers incoming data.
The clock source and PHY straps depend on the chosen parts. MDC/MDIO manages the PHY; it does not carry packet payload.
02 · Transfer
From a TX buffer to a received frame
Follow one frame through ownership, transmission, and a separate peer observation. Compare local errors with corruption seen only by the receiver.
Link100 Mb/s · full duplex
This attempt’s bufferNot reserved
1Free
2CPU
3DMA
4Free
Next: RMII byte timing0xA5 · 100 Mb/s
REF_CLK
TXD[1:0]
—b1:b0—b3:b2—b5:b4—b7:b6
TX_ENNo frame from this attempt yet
2 bits × 50 MHz = 100 Mb/s. Four cycles take 80 ns. This digital inset is not the cable waveform.
Local TX statusNot complete
Separate peer observationNot inspected in this step
No per-frame Ethernet ACK. These are separate observations; their placement does not specify a timing order between devices.
Check the negotiated link. Read the PHY's resolved speed and duplex, then configure the MAC to match before queuing a frame.
Step 1 of 7
Timing and model details
100 Mb/s, full duplex. The RMII inset shows one illustrative 0xA5 payload byte, least-significant dibit first. This is a stage model, not a cable waveform or a timing relationship between local completion and peer reception.
An untagged Ethernet II frame includes addresses and error detection. Small payloads need padding to reach the minimum frame size.
Preamble + SFD8 bytes before the frame
Destination6 BWho receives
Source6 BWho sent
EtherType2 BPayload protocol
Payload40 BExample content
Pad6 BReach minimum
FCS4 BDetect corruption
64 bytes from destination through FCS. Boxes show fields, not proportional lengths.
14 + 40 + 6 + 4 = 64 bytesPreamble/SFD + frame: 72 bytes → 5.76 µs at 100 Mb/sIncluding the 96-bit interframe gap: 6.72 µs per repeated minimum-frame slot
The interframe gap is idle time, not another frame field. The MAC adds padding and FCS only when configured to do so; confirm what the driver expects in memory.
04 · Choose the interface
A network link or a host's peripheral?
Ethernet
Board↔Switch↔Computer
Frames between network peers
USB
Host⇄Device
Host schedules transactions
Choose Ethernet for network access, such as an instrument serving several computers through a switch. Add the required IP and transport stack for those services.
Choose USB for a host-attached device, such as a local measurement accessory. The USB class and endpoints describe how the host communicates with it.
A connector alone does not supply either software model. Both need drivers, buffering, and a defined application protocol.
Advance here or in the transfer above. The highlighted operation and wire state stay on the same step.
Conceptual pseudocodeEthernet driver operations
1ifnotlink_up(): returnLINK_DOWN2desc = try_reserve_tx()
3if desc == NONE: returnBUSY4fill_frame(desc, payload)
5publish_to_dma(desc)
6status = bounded_tx_wait()
7reclaim_released(desc)
8return status // local result only
Step 1 of 7Check the negotiated link
Who drives
Each PHY controls its own transmit pair; no frame queued yet
Sent so far
No frame submitted
Response so far
Local PHY reports 100 Mb/s, full duplex
Link ready · no frame queued
Why this step mattersStep 1 of 7, Check the negotiated link. Read the PHY's resolved speed and duplex, then configure the MAC to match before queuing a frame.
Step 1 of 7
Implementation notes
Conceptual driver operations, not register-level code. publish_to_dma includes the target's cache maintenance, memory barriers, descriptor ownership change, and doorbell. bounded_tx_wait uses a configured deadline; on timeout, recovery must stop DMA access before any buffer is reclaimed. reclaim_released returns only a descriptor and buffer that DMA no longer owns. The success and bad-FCS fixtures both complete locally without a TX error. Peer reception is a separate observation for teaching, never a value returned by this TX API. The displayed stages do not define the relative timing of the two devices.
What to watch for
Common mistakes
Confusing Ethernet with TCP/IP
A MAC address belongs to link-layer delivery. IP addresses, routing, and transport reliability are separate mechanisms above this frame.
Reading TX complete as delivered
Local completion permits buffer reuse. It does not prove peer reception or application processing.
Changing a DMA-owned buffer
Publish visible data, transfer ownership, and wait for release. A timeout alone is not permission to reuse memory.
Treating RMII as cable wiring
RMII joins MAC and PHY on the board. The PHY and magnetics provide the differential cable interface.
Check on the bench
Check negotiated link mode first, then descriptor ownership, local TX status, and peer receive counters or a capture. A valid link LED does not prove frame delivery. To test corruption, inspect the receiver's FCS-error counter; ordinary packet captures may omit frames rejected by the NIC.
Further details and primary sources +
MAC and PHY have different jobs
The Media Access Control block assembles and checks frames. The Physical Layer transceiver encodes the cable signals and reports link state. RMII joins these blocks on the board; it is not the cable protocol.
A switch joins separate links
Each full-duplex link has independent transmit and receive paths. Switches learn source MAC locations and forward frames toward destination ports; unknown unicast and broadcast traffic may be flooded. This lab observes only one link, not a complete switched delivery path.
Completion has a local meaning
The driver publishes a buffer to DMA and waits for ownership to return. TX completion allows reuse under the controller's rules. It is not a peer ACK. A receiver rejects a bad FCS in this fixture; higher-layer protocols decide whether and when to retry.
Example scope
One 100BASE-TX full-duplex link with RMII, an untagged Ethernet II frame, hardware padding/FCS, a preconfigured destination, and no cache-coherency fault. Peer destination filtering passes and receive capacity is available. Bad FCS is injected on the link after local transmission. VLANs, gigabit PHYs, half-duplex collisions, TCP/IP setup, real DMA register layouts, and waveform-level cable encoding are outside this model.
Use CAN when several embedded nodes exchange control and status messages, such as a motor drive, sensor and supervisor. Each node has a controller and a transceiver. They share a bus, and the message identifier decides priority when transmission starts together. CAN FD keeps this arbitration model while allowing more data per frame.
Several nodes share one pair; the dominant bit wins.
01 · Connection
Controllers need transceivers
The controller builds frames. The transceiver connects its logic signals to the shared CAN_H / CAN_L pair.
Node A
CAN controller
TXD ↓ · RXD ↑
Transceiver
Node B
CAN controller
TXD ↓ · RXD ↑
Transceiver
120 Ω · bus end120 Ω · bus end
One linear bus, short node stubs. Terminate the two ends, not every node.
Reference and power are omitted. Choose grounding or isolation to keep every transceiver within its common-mode limits. A CAN controller pin cannot connect directly to the cable.
02 · Transfer
Who gets the next frame?
Follow one frame, let two identifiers compete, or remove the receiver that supplies ACK.
1Queue
2SOF
3Identifier
4Data + CRC
5ACK
6End
Message ID0x120Payload2A 07FormatClassical
SOFID + control2-byte dataCRCACKEOF
Wire order follows the numbered steps. Block width does not represent elapsed time.
ACK slotNot reached
The transmitter sends recessive; a valid receiver can overwrite it with dominant.
Queue a frame. Queuing reserves a controller transmit buffer; it does not mean the frame has reached the bus.
Step 1 of 6
Timing and model details
Logical frame phases, not an analog voltage trace. Only standard 11-bit data frames are compared; stuffed bits, CRC bits and error recovery timing are omitted.
Arbitration stays at the nominal rate. CAN FD changes the frame format and can switch to a faster data phase.
Classical CAN
0–8 data bytesArbitration → data → ACK One configured bit rate
CAN FD
0–64 data bytesNominal → optional faster phase → nominal BRS controls the switch
Each tile represents one byte of maximum payload capacity.
DLC is a code, not always a byte count
Classical · DLC 108 bytesFD · DLC 1016 bytes
FD lengths above 8 are 12, 16, 20, 24, 32, 48 and 64. A larger buffer is not proof that a chosen DLC sends that many bytes. Check the controller’s encoding.
04 · Choose the interface
Messages or a byte stream?
CAN network
SensorDriveSupervisor
Shared pair · message IDs · arbitration
Several nodes publish short control messages. Define priorities, allowed senders and deadlines.
UART link
Device ATX → RX RX ← TXDevice B
A direct byte stream suits a console or module command channel. Add message framing and responses in software.
CAN already frames and checks messages. It still needs an application contract for units, sequence numbers, stale data and command acknowledgment.
UART here means the logic-level, point-to-point link in this guide. Transceivers can adapt UART signaling to other electrical networks.
Why this step mattersStep 1 of 6, Queue a frame. Queuing reserves a controller transmit buffer; it does not mean the frame has reached the bus.
Step 1 of 6
Implementation notes
Conceptual CAN controller operations; firmware queues a frame instead of bit-banging arbitration. The fixture uses standard 11-bit data frames on a correctly terminated high-speed CAN bus. Stuffing, CRC calculation, bit timing, error counters and recovery are not simulated. The no-ACK case is one observed attempt; controller retry policy and a software deadline must be configured. Losing arbitration is normal contention, not a transmission error. An ACK does not identify its sender or prove application consumption.
What to watch for
Common mistakes
Confusing ACK with application delivery
Any active receiver that validates the frame can acknowledge it, even if software does not use that identifier. A command may need an explicit application response.
Terminating every node
This high-speed linear bus uses 120 Ω at each physical end, not at each transceiver. Keep stubs short and validate the selected physical-layer design.
Treating arbitration loss as a fault
The lower-priority sender becomes a receiver and waits for another opportunity. Persistent higher-priority load can delay it, so budget deadlines and retries.
Enabling FD on a Classical-only network
Check every controller, transceiver and timing configuration. Classical-only nodes may signal errors when an FD frame arrives.
Check on the bench
Inspect identifier, payload, ACK and error status. Trigger simultaneous frames with different IDs, then remove the acknowledging receiver. Check both physical terminations, differential signaling, bit timing, retry limits and transmit completion status.
Further details and primary sources +
Arbitration belongs to the controller
At a bus opportunity, multiple controllers may start together. Each compares its transmitted bit with the bus. During arbitration, sending 1 and observing 0 means losing access. The winner continues intact; this is not a damaged frame.
A message ID is not a node address
The network defines the meaning and priority of identifiers. Receivers use acceptance filters to select messages for software. Assign identifiers and transmitter ownership deliberately; equal IDs with different data are not resolved by identifier arbitration.
CAN FD changes frame capacity
Classical CAN carries up to 8 data bytes. CAN FD supports lengths through 64 bytes using a different DLC mapping and can switch rate within a frame. Controllers and transceivers must support the chosen network; ordinary Classical-only nodes can disrupt FD traffic.
Example scope
Standard 11-bit data frames on a high-speed CAN bus. Arbitration is shown without stuffed bits. The 500 kbit/s nominal and 2 Mbit/s FD data rates are fixtures, not guarantees for a cable length or transceiver. Extended IDs, remote frames, CRC calculation, detailed error confinement, bus-off recovery and higher-layer protocols are outside the simulation.
Use SD memory to read and write stored sectors, and SDIO to control a compatible peripheral such as a wireless module. Both use host-driven clocks, but storage addresses and function registers are different things. Start with a sector read, then switch to CMD52 to see a register byte return without a DAT transfer.
The same bus family serves storage or I/O devices.
01 · Connection
One command line, four data lines
The host supplies CLK. Both sides take turns on CMD; payload uses the separate DAT bus.
Host controllerCard / I/O device
CLK→Host supplies timing
CMD↔Command, then response
DAT3…0Read ← · write →
Power / GNDSupply + common reference
Six main signals in four-bit mode. Power, ground and any card-detect switch are additional connections.
For the read shown hereHost → CMD17 requestCard → R1 response on CMDCard → payload on DAT3…0
The drawing shows native SD after initialization. CMD/DAT pull-ups, voltage, pin mux and routing must follow the board and device requirements. This is a signal map, not a wiring schematic.
02 · Transfer
A sector read and a register read
Follow the command on CMD, then see whether the result uses DAT or returns inside the response.
1Prepare
2CMD17
3R1
4Payload
5CRC
6Finish
Arm a private receive bufferPhase 1 of 6
CLKHost · 12 MHz
CMD
Released
DAT3…0
Released
Receive bufferPrivate · not published0 payload bytes received
CLK shows the timing source, not an elapsed-time scale. Response delays and clock gating are not drawn.
Arm a private receive buffer. Reserve 512 bytes and arm reception before requesting the block, so arriving data has somewhere to go.
Step 1 of 6
Timing and model details
Native SD · already initialized · 4-bit SDR · 12 MHz fixture. One 512-byte SDHC read or one SDIO register byte. Phase widths are not durations.
A native SD read in four-bit SDR mode carries one bit per DAT wire on each sampling edge. Two such samples assemble one byte.
SampleD3D2D1D0
First · A1010
Next · 50101
D3…D0 means DAT3…DAT0. The most-significant nibble of this byte arrives first.
512 × 8 ÷ 4 = 1,024 clocksPayload only · excludes command, response, start/end bits, CRC and waits
4-bit native SD1,024 clocks
1-bit SPI payload4,096 clocks
At the same clock frequency, four lanes carry this payload in one quarter of the clocks. This is not a file-speed guarantee: device delays, command overhead and software still count.
04 · Choose the interface
Storage sectors or I/O registers?
SD memoryCMD17 → R1 → DAT block
Read a stored sector. A filesystem gives those bytes names, directories and file meaning.
SDIO · one registerCMD52 → R5 with one byte
Read a function’s status or control register. No separate DAT payload follows.
SDIO · larger transferCMD53 → R5 → DAT payload
Move a byte count or blocks for an I/O function. Choose fixed-address FIFO or incrementing-address access.
A compatible connector is not enough. The host driver must support the device’s command set, initialization and function behavior.
A conventional SPI link uses one incoming data wire. Native SD uses a distinct command line and can add data lanes. Device support and available pins decide which mode is usable.
Why this step mattersStep 1 of 6, Arm a private receive buffer. Reserve 512 bytes and arm reception before requesting the block, so arriving data has somewhere to go.
Step 1 of 6
Implementation notes
The card is already initialized, selected and in 4-bit Default Speed mode; the host matches its width and voltage. The fixture uses a 12 MHz clock, not an initialization clock. Arm the receive path before issuing CMD17. The controller handles response CRC, four data-line CRC16 checks and transfer timeouts; data.ok includes successful completion and CRC. Abort must stop hardware/DMA before releasing the private buffer. Register flags, cache maintenance, timeout values and recovery are controller-specific. A single-block read does not use a write-programming busy phase or require CMD12 to end a successful transfer.
What to watch for
Common mistakes
Mixing block and byte addresses
SDHC block 8 uses command argument 8. SDSC uses byte-address units; the equivalent 512-byte sector starts at 4096.
Widening only one end
Initialize and configure the card as well as the host. Four-bit mode requires agreement on DAT0 through DAT3.
Trusting DMA completion alone
Check command status, data completion and CRC before publishing the block. A received buffer can still contain invalid data.
Treating every SD device as storage
SDIO function registers use CMD52/CMD53. Check the module’s register map, pin mux, pull-ups and voltage requirements.
Check on the bench
Decode the command and its response separately from the DAT payload. Confirm width at both ends, the selected address units, the received byte count and all CRC results. Force a missing response and corrupt data before checking recovery.
Further details and primary sources +
Initialize before widening the bus
Discover the device and its capabilities, select it, and configure both ends for the same width and timing mode. This lab starts after initialization; switching only the host to four bits does not configure the card.
Separate responses from data
CMD17 returns R1 on CMD, then the block on DAT. Native SD read data includes CRC16 on each active data line. DAT0 busy signaling is relevant to operations such as write programming; it is not an extra phase of the read shown here.
Choose memory or I/O commands
CMD17 reads a memory block. SDIO CMD52 accesses one function-register byte in its R5 response. CMD53 carries a byte count or blocks on DAT, with fixed-address FIFO or incrementing-address access as required by the function.
Example scope
Initialized and selected native-SD devices, 3.3 V, four-bit Default Speed SDR, with a fictional 12 MHz operating clock supported by both ends. The memory fixture is SDHC; the I/O fixture is an enabled SDIO function. Initialization, write programming, interrupts, UHS, DDR, SD Express and filesystems are outside the trace. Diagrams are not to scale.
