What this tests
RTL design interviews ask you to translate behavior into clocked hardware while making every state, priority, width, and timing assumption explicit. The strongest answers do more than produce legal SystemVerilog.
Behavior to synthesizable hardware
RTL Design Interview Questions
How to practice
Work through this collection by first describing the interface contract and cycle-level behavior, then choosing state and datapath structures. Check boundary conditions such as full and empty, wraparound, backpressure, signed arithmetic, and illegal states before writing code.
Topic breakdown
What to be ready to explain
Combinational intent
Reason about complete assignment, priority, arithmetic width, signedness, and the structure a synthesizer will infer.
- Muxes
- Arithmetic
- Latch avoidance
- Combinational loops
Sequential behavior
Define reset, enables, state transitions, counters, and simultaneous-event priority at exact clock boundaries.
- Registers
- Counters
- FSMs
- Reset
Flow-controlled systems
Preserve data and ordering through FIFOs, pipelines, arbiters, and ready-valid interfaces under backpressure.
- FIFOs
- Ready-valid
- Pipelines
- Arbitration
Curated practice links
Questions to work through
Permanent bank numbers and direct links make it easy to continue in the live question bank.
- Q002Build a synchronous FIFO and race-free BFM
Explain the key FIFO and BFM decisions, assumptions, and checks.
RTL Design · Medium - Q296Build a reloadable countdown timer
Explain the key Counter and Pulse decisions, assumptions, and checks.
RTL Design · Easy - Q861Detect overlapping 1011 sequences
Explain the key Sequence detector and Mealy FSM decisions, assumptions, and checks.
FSMs · Medium - Q663Pipeline a parameterized barrel rotator
Explain the key Barrel rotator and Pipelining decisions, assumptions, and checks.
RTL Design · Hard - Q003Choose a safe clock-domain crossing strategy
Explain the key CDC and Metastability decisions, assumptions, and checks.
Clock Domain Crossing · Medium - Q005Synchronize reset release in each clock domain
Explain the key Reset and Async assert decisions, assumptions, and checks.
Reset Design · Easy - Q231Register a glitch-free decoded enable
Explain the key Decode and Clock enable decisions, assumptions, and checks.
RTL Design · Easy - Q434Absorb ready/valid backpressure with a skid buffer
Explain the key Skid buffer and Ready/valid decisions, assumptions, and checks.
RTL Design · Hard - Q636Detect and recover an upset one-hot FSM
Explain the key One-hot and SEU decisions, assumptions, and checks.
Reliable RTL · Medium - Q446Reverse a physical bus at the lane boundary
Explain the key Bit reversal and Packed vectors decisions, assumptions, and checks.
RTL Design · Easy - Q962Count active lanes in a predicate mask
Explain the key Population count and Reduction decisions, assumptions, and checks.
RTL Design · Easy - Q502Increment a four-digit BCD counter
Explain the key BCD and Ready/valid decisions, assumptions, and checks.
RTL Design · Easy - Q947Search a synchronous calibration ROM
Explain the key Binary search and Synchronous ROM decisions, assumptions, and checks.
RTL Design · Easy - Q853Vote across redundant state monitors
Explain the key Majority voter and Fault tolerance decisions, assumptions, and checks.
RTL Design · Easy - Q039Stably sort records in a local cache-line buffer
Explain the key Stable sort and Single-port memory decisions, assumptions, and checks.
RTL Design · Medium - Q586Control a tiny exact-LRU associative cache
Explain the key LRU and Associative lookup decisions, assumptions, and checks.
RTL Design · Medium - Q335Schedule bank commands with accepted-slot cooldown
Explain the key Scheduler and Cooldown decisions, assumptions, and checks.
RTL Design · Medium - Q757Decode Z wildcards without hiding X
Explain the key Case statements and X propagation decisions, assumptions, and checks.
RTL Design · Easy - Q924Diagnose storage from an incomplete always_comb block
Explain the key Combinational logic and Latch inference decisions, assumptions, and checks.
RTL Design · Easy - Q640Implement a parameterized binary-to-Gray converter
Explain the key Gray code and Combinational logic decisions, assumptions, and checks.
RTL Design · Easy - Q548Code an asynchronously reset register with enable
Explain the key Flip-flop and Reset decisions, assumptions, and checks.
RTL Design · Easy - Q518Build a parameterized N-to-1 multiplexer
Explain the key Multiplexer and Parameters decisions, assumptions, and checks.
Combinational RTL · Medium - Q799Compare synchronous and asynchronous reset
Explain the key Reset and Timing decisions, assumptions, and checks.
RTL Design · Easy - Q413Combinational versus sequential logic
Explain the key Combinational RTL and Sequential RTL decisions, assumptions, and checks.
RTL Design · Easy - Q716Why an FSM infers a latch
Explain the key Latch inference and Synthesis decisions, assumptions, and checks.
FSMs · Easy - Q187Synchronous rising-edge detector
Explain the key Edge detector decisions, assumptions, and checks.
Sequential RTL · Easy - Q892Implement a synchronous FIFO with exact boundary behavior
Explain the key FIFO and Ready-valid decisions, assumptions, and checks.
RTL Design · Medium - Q643Count consecutive zeros with saturation
Explain the key RTL decisions, assumptions, and checks.
RTL Design · Easy - Q398Convert a synchronous level into a one-cycle rising pulse
Explain the key RTL decisions, assumptions, and checks.
RTL Design · Easy - Q570Implement a four-requester round-robin arbiter
Explain the key Arbitration decisions, assumptions, and checks.
RTL Design · Medium