1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ861

Q861DesignDVASIC interview problem

Detect overlapping 1011 sequences

TechniquesSequence detectorMealy FSMOverlapGolden model

DifficultyMedium

TopicFSMs

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Design a serial detector for the pattern 1011 with overlap enabled. Assert match in the cycle that the final bit is accepted, and provide a bus functional model (BFM) check based on a sliding-window model rather than duplicating the FSM.

Example input and output

Use this case to check your interpretation

Input

accepted bits=[1,0,1,1,0,1,1] with arbitrary valid gaps

Output

match pulses on accepted bits 4 and 7

Explanation

The sliding accepted-bit windows are 1011 at both endpoints in 1011011; valid gaps hold state and do not create positions.

Requirements (4)

Sample one input bit whenever valid_in is high and hold state across valid gaps.
Detect both occurrences in 1011011.
Assert match only for a valid final bit and for one cycle per occurrence.
The checker must compare against the last four accepted bits and preserve a short failure trace.