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DescriptionQ586
Q586DesignArchASIC interview problem

Control a tiny exact-LRU associative cache

TechniquesLRUAssociative lookupReplacement policy
DifficultyMedium
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

Build a 2-to-8-way fully associative cache controller with serialized read (GET) and write/update (PUT) commands, exact least-recently-used (LRU) replacement, and a stallable one-entry response channel.

Example input and output

Use this case to check your interpretation
Input
2-way empty cache: PUT A, PUT B, GET A, PUT C
Output
GET A hits and makes A MRU; PUT C evicts B and reports B's tag/data
Explanation

After the hit, B is exact LRU; the full-cache insertion replaces only that way while A and C remain unique valid tags.

02

Requirements (4)

  • A GET hit returns data and becomes most recently used (MRU); a GET miss leaves recency unchanged.
  • PUT updates a hit, otherwise uses the lowest-index invalid way before evicting the exact LRU way.
  • Keep tags unique among valid ways and report evicted tag/data only for a full-cache replacement.
  • Hold every response field and all cache metadata stable while a response is stalled.