1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ548

Q548DesignASIC interview problem

Code an asynchronously reset register with enable

TechniquesDesignSystemVerilogFlip-flopResetClock enable

DifficultyEasy

TopicRTL Design

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Write parameterized RTL for a register that samples data when enable is high, holds its value otherwise, and asserts reset asynchronously low.

Module declarationSystemVerilog

module enabled_register #(
  parameter int W = 8
) (
  input  logic         clk,
  input  logic         rst_n,
  input  logic         en,
  input  logic [W-1:0] d,
  output logic [W-1:0] q
);

Example input and output

Use this case to check your interpretation

Input

W=8; rst_n=1, en=1, d=8'h5A at a rising clock edge

Output

q=8'h5A after the nonblocking update

Explanation

With reset inactive and enable asserted, the edge samples d into q. If enable were low, q would retain its prior value.

Requirements (4)

Assert reset on negedge rst_n without waiting for a clock edge.
Model normal reset release behavior at the next posedge clk.
Hold q when en is low.
Use nonblocking assignments for q.