1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ636

Q636DesignDVASIC interview problem

Detect and recover an upset one-hot FSM

TechniquesOne-hotSEUIllegal stateSafe recovery

DifficultyMedium

TopicReliable RTL

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Protect a 16-state one-hot control FSM against single-event upsets. Detect zero-hot and multi-hot encodings with shallow logic, force a safe recovery state, and add an assertion for verification.

Example input and output

Use this case to check your interpretation

Input

16-bit one-hot state=16'b0000_0000_0000_0010; then an upset creates 16'b0000_0000_0000_0110

Output

normal next state is 16'b0000_0000_0000_0100; the upset asserts error and the next edge forces SAFE 16'b0000_0000_0000_0001

Explanation

Two asserted state bits are illegal even though a binary encoding might interpret a flipped bit as another valid state.

Requirements (4)

Treat exactly one asserted bit as legal; all-zero and two-or-more-hot values are illegal.
On detection, override normal next-state logic and recover to SAFE on the next edge.
Expose an error indication so the event can be logged or escalated.
Explain why a binary-state bit flip can silently land on another valid code.