DescriptionQ663
Q663DesignDVASIC interview problem
Pipeline a parameterized barrel rotator
TechniquesBarrel rotatorPipeliningParameterizationGolden model
DifficultyHard
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Design a fully parameterized left/right barrel rotator split across two registered stages. Pipeline valid with the data and write a BFM that predicts rotations and checks the fixed latency.
Example input and output
Use this case to check your interpretationInput
W=8; accept x=8'b1001_0001, direction=left, shift=3 at cycle0Output
out_valid at cycle2 with 8'b1000_1100Explanation
The two registered stages implement rotate-left-three modulo eight and pipeline valid with every data/control slice.
02
Requirements (4)
- Support any W greater than zero, including W = 1, and reduce shift amounts modulo W.
- Apply lower shift-control bits before the first register and upper bits before the output register.
- Pipeline direction, remaining shift bits, and valid alongside data.
- The predictor must handle shift zero without evaluating a shift by the full word width.