DescriptionQ231
Q231DesignASIC interview problem
Register a glitch-free decoded enable
TechniquesDecodeClock enableGlitchRegistered output
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01
Problem
Generate valid when a two-bit input equals 01 or 10. The signal will control downstream sequential logic, so make the decoded result cycle-aligned and glitch-free rather than using it to gate a clock.
Example input and output
Use this case to check your interpretationInput
two-bit inputs by clock=[00,01,11,10] after resetOutput
registered valid one cycle later=[0,1,0,1]Explanation
Only 01 and 10 decode true, and registering the decode prevents between-edge input transitions from creating a clock-gating glitch.
02
Requirements (4)
- Register valid on the functional clock.
- Never create a derived clock with combinational decode logic.
- Reset valid to a known inactive value.
- State the one-cycle latency introduced by registering the decode.