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DescriptionQ446
Q446DesignASIC interview problem

Reverse a physical bus at the lane boundary

TechniquesBit reversalPacked vectorsCombinational logic
DifficultyEasy
TopicRTL Design
LanguageSystemVerilog
Requirements4 checkpoints
01

Problem

A board routes a peripheral bus in reverse bit order. Build a parameterized combinational adapter whose output bit i is input bit W - 1 - i.

Example input and output

Use this case to check your interpretation
Input
W=8; input=8'b1101_0010
Output
output=8'b0100_1011
Explanation

Output bit i is wired directly from input bit 7-i, making this a bit reversal rather than a byte-endian conversion.

02

Requirements (4)

  • Treat this as bit reversal, not a byte swap or numeric endian conversion.
  • Support every static width W >= 1, including odd widths and W = 1.
  • Drive every output bit on every evaluation and infer no state.
  • Use only compile-time-bounded, synthesizable wiring.