1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ187

Q187DesignAppleASIC interview problem

Synchronous rising-edge detector

TechniquesDesignEdge detectorSequential RTL

DifficultyEasy

TopicSequential RTL

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Write synthesizable SystemVerilog that produces one clock-cycle pulse when a clock-synchronous input changes from 0 to 1. If the source is asynchronous, it must be synchronized before this block.

Module declarationSystemVerilog

module rise_detector (
  input  logic clk,
  input  logic rst_n,
  input  logic in_sync,
  output logic rise_pulse
);

Example input and output

Use this case to check your interpretation

Input

sampled in_sync = 0, 0, 1, 1, 0, 1

Output

rise_pulse = 0, 0, 1, 0, 0, 1

Explanation

A pulse is generated only when the current sample is high and the stored previous sample is low.

Requirements (4)

Sample in_sync only on rising clock edges.
Reset the stored history and pulse output to zero.
A signal held high for multiple clocks produces one pulse only.
Do not create a combinational asynchronous path from the input to rise_pulse.