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Stimulus · checking · closure evidence

Design Verification Engineer Interview Questions

Trace transactions through a reusable UVM environment, then prove behavior with scoreboards, assertions, coverage, constrained stimulus, protocol checks, and closure evidence.

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Showing 38 of 38All questions visible
  1. Q001SystemVerilogBlocking and nonblocking assignmentSystemVerilog · Basic schedulingEasy
  2. Q016Data StructuresPacked and unpacked arraysSystemVerilog · Array formsEasy
  3. Q008UVM Componentsuvm_object versus uvm_componentUVM · Class roles and constructionEasy
  4. Q252UVM ComponentsBuild and connect phasesUVM · Phase lifecycle and orderingEasy
  5. Q044UVM ComponentsConfig_db virtual interface distributionUVM · Configuration scoping and precedenceEasy
  6. Q263UVM ComponentsSequencer-driver connectionUVM · Pull protocol handshakeEasy
  7. Q170UVM ComponentsAnalysis port semanticsUVM · Analysis distributionEasy
  8. Q053Reference ModelsOut-of-order scoreboard matchingUVM · Checking architectureMedium
  9. Q297UVM ComponentsDrive a ready/valid interface correctlyUVM · DriverMedium
  10. Q602UVMConnect a UVM monitor to a scoreboardDV · UVMMediumP
  11. Q904VerificationExplain what functional coverage measuresDV · CoverageEasyP
  12. Q1104Functional CoverageBuild Traceable Verification Items from a SpecificationDV · DesignMediumP
  13. Q299Functional CoverageCoverpoint binsSystemVerilog · Functional coverageEasy
  14. Q395Functional CoverageIgnored and illegal binsSystemVerilog · Functional coverageEasyP
  15. Q329Functional CoverageArrayed coverage binsSystemVerilog · Advanced coverageMediumP
  16. Q065Formal VerificationProve an arbiter avoids deadlock and livelockDeadlock · LivelockHard
  17. Q126Temporal ChecksAssert an integer square-root pipelineDV · SVAHard
  18. Q046Temporal ChecksProve an elastic one-hot checkerDV · SVAHard
  19. Q374SystemVerilogConcurrent assertion schedulingSystemVerilog · Scheduling regionsEasyP
  20. Q082Temporal ChecksSystemVerilog Assertions (SVA) implicationSystemVerilog · Assertion timingEasy
  21. Q666Temporal ChecksSVA repetitionSystemVerilog · Assertion timingEasyP
  22. Q396ConstraintsBias burst lengths by rangeRandomization · distEasyP
  23. Q259ConstraintsConstrain a size-aligned addressRandomization · AlignmentEasy
  24. Q973ConstraintsEnforce uniqueness within each groupRandomization · Conditional uniquenessMediumP
  25. Q958ConstraintsRandomize weighted onehot-or-zero requestsRandomization · OnehotMediumP
  26. Q691ConstraintsConstrain a DMA transfer to one 4KB pageSystemVerilog · ConstraintsMediumP
  27. Q002Waveform DebuggingValid Drops During a StallDV · Waveform DebuggingEasy
  28. Q272Temporal ChecksCheck hold while stalledHandshake · ProtocolEasy
  29. Q140Temporal ChecksMonitor ready/valid without SVADV · DesignMedium
  30. Q017Protocol CheckingAPB Protocol Monitor without SVADV · APBMedium
  31. Q035Waveform DebuggingAXI Write Address Changes While StalledDV · Waveform DebuggingMedium
  32. Q620Waveform DebuggingAXI Read Responses Reverse Two Requests with the Same IDDV · Waveform DebuggingHardP
  33. Q019Waveform DebuggingPipeline Returns the Wrong TagDV · Waveform DebuggingMedium
  34. Q029Waveform DebuggingUnknown Output After ResetDV · Waveform DebuggingEasy
  35. Q116Waveform DebuggingRead Attempt on an Empty FIFODV · Waveform DebuggingEasy
  36. Q125Waveform DebuggingAcknowledge Without an Outstanding RequestDV · Waveform DebuggingEasy
  37. Q036Clock Domain CrossingModel a CDC-safe asynchronous FIFODesign · DVHard
  38. Q785Clock and Reset DomainsImplement a coordinated-reset depth-16 asynchronous FIFODV · DesignHardP

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  • Easy20
  • Medium12
  • Hard6

Related learning

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These are the guides most often linked by questions in this collection.

  1. 01Transfer ContractsReview ready-valid, request-acknowledge, APB, and AHB transfer rules.5
  2. 02Coverage Bins and CrossesReview covergroups, bins, transitions, crosses, exclusions, and model size.3
  3. 03Relational and Array ConstraintsReview equations, ordering, arrays, uniqueness, reductions, alignment, and nonoverlap.3
  4. 04SVA Timing and OperatorsReview implication, endpoints, delays, repetition, and exact sampled-edge timing.3
  5. 05UVM Factory and StimulusReview factory overrides, configuration, sequences, sequencers, and drivers.3
  6. 06CDC and ClocksReview crossing protocols, metastability risk, Gray pointers, clock relationships, and gating.2
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