RTL intent to signoff margin

Synthesis and Timing Closure

Autopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.

Read timing evidence instead of chasing summary numbers, distinguish constraint bugs from real path failures, and choose repairs that preserve function while improving total QoR.

Updated July 20266 connected chaptersInteractive labs + worked examples

Path autopsy · functional mode · SS 0.72 V 125 °C

One path. Five models. One signoff verdict.

Follow u_issue/req_q[0] through eligibility logic and four priority muxes to u_issue/next_q[2]. Each implementation stage replaces an estimate with stronger evidence.

Startpoint req_q[0]/CKLogic qualify → MUX2 × 4Endpoint next_q[2]/DSetup slack −0.18 ns

LaunchFF_LtCQ max · 0.09 ns

CaptureFF_Csetup · 0.06 ns

Propagated clock root

Llaunch · 0.10 nsLcap · 0.14 ns

report_timing · max pathRequired − arrival = slack

MeasureExpressionResult

Data arrival0.09 + 0.870.96 ns

Data required0.85 + 0.04 − 0.06 − 0.050.78 ns

Setup slack0.78 − 0.96−0.18 ns

The full report expands these normalized terms into launch latency, library arcs, extracted interconnect, capture latency, uncertainty, and setup time. The chapter autopsy reconciles every increment.

Open the interactive timing report →

RTL intent becomes timed structure

Synthesis is inference followed by legal, library-aware optimization.

Read the mapped structure as the tool’s interpretation of the RTL, not as an inevitable implementation.

issue_select.svElaborated RTL

always_comb begin
  next = hold;
  for(int i = 0; i < 4; i++)
    if(req[i] && !busy[i])
      next = payload[i];
end

The loop is priority logic. The final assignment wins, so elaboration creates a serial select cone unless the intent or coding structure changes.

01Elaborateparameters + generates

Resolve hierarchy, widths, constant conditions, and signedness.

02Inferflops · muxes · arithmetic

Recognize state, enables, comparators, adders, and memories.

03OptimizeBoolean + sequential

Propagate constants, share or duplicate logic, and retime when legal.

04Maplibrary cells

Choose real arcs, drive strengths, Vt flavors, and legal macros.

Mapped cone4 priority MUX2 stages · highest index wins

Mapped cell delay0.38 nsEstimated net0.11 nsFirst questionIs the serial priority intentional?

State inference

Every register, latch, and memory must be intentional.

Review inferred clocks, enables, resets, RAM modes, latch reports, width truncation, signed operations, and combinational loops before timing optimization hides the original symptom.

Optimization boundary

Preserve observability only where the architecture needs it.

Hierarchy, dont-touch directives, test structures, and debug visibility can block duplication, retiming, and constant propagation. Each preservation constraint spends QoR.

Evidence

Compare RTL intent, mapped topology, and equivalence.

Lint and elaboration explain the source. Synthesis reports explain the structure. Formal or logical equivalence proves that legal transformations preserve the defined behavior.

Completeness before optimization

A timing graph is only as trustworthy as its clocks and path intent.

Treat constraints as an executable interface specification with coverage, ownership, and review evidence.

Selected constraint group: Clock roots. Does every sequential endpoint inherit the intended waveform?

Constraint ledgerClock roots

Question the SDC must answer

Does every sequential endpoint inherit the intended waveform?

create_clockcreate_generated_clockset_clock_latencyset_clock_uncertainty

Evidence: List all clocks, their sources, periods, waveforms, generated-clock masters, and propagated status.
Failure if absent or broad: A missing generated clock can time logic against the wrong edge or leave a domain unconstrained.

Pre-closure gate

Do not optimize until the report universe is complete.

Coverage areaRelease conditionEvidence to inspect

Clock coverage0 unconstrained sequential endpointsReport all clock pins and no-clock checks

I/O coverageEvery legal port has min and max budgetsReconcile against the system timing budget

Interaction matrixEvery clock pair classifiedSynchronous, asynchronous, or exclusive with rationale

ExceptionsApplied, scoped, and independently justifiedReview ignored and overridden exceptions

ModesEvery case-analysis branch ownedProve disabled arcs and test controls are intentional

Path sanityTop paths match architectureSample startpoints, endpoints, and edge pairing

Reconcile every picosecond

Autopsy the path before prescribing the ECO.

A timing report is a causal chain: launch edge, data arrival, capture edge, requirement, adjustments, and verdict.

report_timing -delay_type maxfunc_ss_cmax · group core_clk

clock core_clk (rise edge)0.0000.000

clock network delay (propagated)+0.1000.100

req_q[0]/CK → Q+0.0900.190

AOI21_X2 / MUX2_X1 × 4+0.4200.610

net RC + coupling delta+0.4501.060

next edge + capture clock latency0.850 + 0.1400.990

library setup + uncertainty−0.1100.880

slack (VIOLATED)−0.180

Selected timing report region: Data path. Separate cell arcs from nets before choosing a repair.

Setup + hold edge lab

Change one term and watch both timing contracts move.

Setup slackT + (L_cap − L_launch) − (tCQ_max + tPD_max + t_setup + U_setup)−0.180 ns

Hold slacktCQ_min + tCD_min − ((L_cap − L_launch) + t_hold + U_hold)+0.040 ns

latest / earliest datasetup aperturehold requirementcapture edge

Clock relationship

Period TnsLaunch latencynsCapture latencynsSkew Lcap − Llaunch+0.040 ns

Maximum path · setup

tCQ maxnstPD maxnsSetup timensSetup uncertaintyns

Minimum path · hold

tCQ minnstCD minnsHold timensHold uncertaintyns

Positive capture skew helps setup but hurts hold.In this convention, increasing Lcap − Llaunch adds setup margin and subtracts the same first-order amount from hold margin.

Estimates become geometry

Placement, CTS, extraction, SI, and OCV change what the path means.

Compare stages using the same endpoints so model improvements are not mistaken for design regressions.

SRAM A

SRAM B

FF_L

FF_C

congestion channel

coupled aggressor

Selected implementation stage: Extracted signoff. Extracted resistance, capacitance, crosstalk delta delay, slew degradation, and signoff variation decide the final path.

Pre-physical

Use estimates to expose architectural risk early.

Logic depth, fanout, macro choice, and target frequency
Wire-load or placement-independent net estimates
Ideal or estimated clocks
Coarse variation and congestion prediction

placementclock treeextracted RCSI + OCV

Post-route signoff

Use extracted evidence to make the final verdict.

Actual cell locations, legal routes, and pin access
Propagated clock latency, skew, and reconvergence
Coupled resistance/capacitance and slew
AOCV/POCV, crosstalk, CPPR, and MMMC views

Repair the mechanism, not the symptom

Every timing ECO moves setup, hold, power, area, and risk.

Choose the highest-leverage layer that can still change, then remeasure the whole affected timing neighborhood.

Setup-slack waterfallRestructure logic

Baseline−0.180 ns

ECO contribution+0.190 ns

Reanalyzed+0.010 ns

Selected repair: Restructure logic. Setup change +0.190 ns; hold change −0.010 ns.

Setup+0.190 ns

Hold−0.010 ns

Power↔ or ↓ activity

Areadepends on sharing

1Constraint

Prove the path and analysis view are real.

2Architecture

Pipeline, parallelize, or change the protocol while flexibility remains.

3Logic

Restructure depth, fanout, arithmetic, and sharing.

4Physical

Place, buffer, route, size, and tune Vt with local evidence.

5Clock + min delay

Use skew and hold ECOs only with coupled-view checks.

6Re-signoff

Repeat MMMC, noise, power, DRC, and equivalence evidence.

MMMC evidence and release discipline

Signoff means every legal scenario closes without breaking equivalence or PPA.

One green corner is not a tapeout decision. Build a reviewable matrix of modes, libraries, RC corners, checks, and owners.

Selected analysis view: Functional, Setup, WNS −0.18 ns.

Beyond register-to-register data

Four edge contracts still need dedicated signoff views.

01Recovery

Reset deassertion must settle before the active edge. Treat it like a setup-style maximum-delay check.

02Removal

Reset deassertion must not change too soon after the active edge. Treat it like a hold-style minimum-delay check.

03Pulse width

High and low clock phases must each exceed the library minimum after propagated-tree distortion.

04Gating check

The enable must remain stable across the clock-gate latch aperture so no runt pulse reaches the tree.

Release evidence

Close the design, not only the setup table.

Timing

All setup, hold, recovery/removal, pulse-width, and gated-clock checks close in every required view.

Constraints

No unintended unconstrained endpoints; clocks, exceptions, case analysis, and scenario bindings are reviewed.

SI + variation

Crosstalk, extracted RC, derates, CPPR, noise, and variation models match the signoff methodology.

Equivalence

RTL-to-synthesis and post-ECO logical equivalence pass with intentional transforms explicitly handled.

Physical

DRC, LVS, antenna, density, electromigration, IR drop, and clock checks satisfy release criteria.

PPA

Frequency closure does not exceed dynamic power, leakage, area, congestion, or reliability budgets.

Test + low power

Scan, at-speed test, isolation, retention, reset, and power-state timing views remain legal.

Reproducibility

Tool versions, libraries, corners, constraints, waivers, reports, and checksums are archived.

Primary references

Constraint and closure methodology

These AMD references are FPGA-oriented, but their disciplined treatment of clocks, exceptions, path coverage, methodology checks, and closure baselines transfers directly to ASIC timing reasoning. ASIC signoff additionally depends on foundry libraries, extracted parasitics, variation, SI, IR/EM, and physical-verification flows; OpenSTA provides an ASIC-oriented, inspectable reference implementation for Liberty, SDC, SPEF, SDF, and gate-level timing analysis.

AMD UG903Using ConstraintsClocks, I/O delays, exceptions, and constraint scoping ↗AMD UG949UltraFast Design MethodologyBaseline, methodology checks, QoR, and design closure ↗OpenROAD projectOpenSTA timing engineLiberty, SDC, SPEF, SDF, corners, and gate-level STA ↗

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.

01Why can positive capture skew help setup but hurt hold?

A later capture clock gives the maximum-delay path more time before the next capture edge, increasing setup margin. The same later edge makes it easier for the earliest new data to reach the destination too soon relative to that capture event, reducing hold margin. Useful skew is therefore a coupled optimization, not free setup slack.

02Why is a clean pre-route timing report not final evidence?

Before placement and routing, net delays, congestion, coupling, and clock-tree latency are estimated. Signoff uses extracted interconnect, propagated clocks, variation and uncertainty models, and the required mode/corner combinations. Early timing is valuable for direction, but only the implemented timing model represents the final physical path.

03What should you check before fixing negative slack?

Verify the clocks and generated clocks, modes, I/O delays, uncertainty, exceptions, case analysis, path grouping, and whether the reported startpoint and endpoint match architectural intent. Then inspect the full path and physical context. Optimizing a path created by a bad constraint wastes effort; cutting a real failing path hides a bug.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Explain what STA provesSeparate timing-graph evidence from functional behavior.Classify path boundariesIdentify legal startpoints, endpoints, and clock relationships.Calculate maximum frequencyUse a setup path with skew and uncertainty correctly.Reason about capture skewTrack opposite effects on setup and hold.Pipeline a critical pathTrade architectural latency for shorter combinational depth.Choose coupled timing ECOsImprove setup and hold without losing QoR or correctness.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.