Part 1 · Synthesis and constraints
Map RTL and define the timing problem
Follow elaboration, inference, optimization, and technology mapping, then constrain clocks, I/O, uncertainty, relationships, modes, corners, and legitimate exceptions.
RTL intent to signoff margin
Synthesis and Timing Closure
Autopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.
Read timing evidence instead of chasing summary numbers, distinguish constraint bugs from real path failures, and choose repairs that preserve function while improving total QoR.
Updated July 20266 connected chaptersInteractive labs + worked examples
Start Part 1
Part 2 · Path analysis and physical reality
Autopsy timing paths in their physical context
Read launch, data, capture, requirements, derates, and slack, then account for placement, CTS, routing, parasitics, variation, crosstalk, and congestion.
Part 3 · Closure and signoff
Choose coupled ECOs and close every signoff view
Select architectural, logical, sizing, placement, routing, and skew repairs while protecting hold, power, area, equivalence, test modes, and MMMC signoff.
Path autopsy · functional mode · SS 0.72 V 125 °C
One path. Five models. One signoff verdict.
Follow u_issue/req_q[0] through eligibility logic and four priority muxes to u_issue/next_q[2]. Each implementation stage replaces an estimate with stronger evidence.
Startpoint req_q[0]/CKLogic qualify → MUX2 × 4Endpoint next_q[2]/DSetup slack −0.18 ns
LaunchFFLtCQ max · 0.09 ns
01
Elaborated RTL
priority depth · 4Intent and inferred state02Mapped gates
cell arc · 0.38 nsLibrary-aware delay03Placed
estimated net · 0.19 nsLocation enters the model04CTS
skew · +0.04 nsPropagated clocks05Extracted route
logic + RC + SI · 0.87 nsSignoff data arrivalCaptureFFCsetup · 0.06 ns
Propagated clock root
Llaunch · 0.10 nsLcap · 0.14 ns
report_timing · max pathRequired − arrival = slack
Measure
ExpressionResultData arrival
0.09 + 0.870.96 nsData required
0.85 + 0.04 − 0.06 − 0.050.78 nsSetup slack
0.78 − 0.96−0.18 nsThe full report expands these normalized terms into launch latency, library arcs, extracted interconnect, capture latency, uncertainty, and setup time. The chapter autopsy reconciles every increment.
Open the interactive timing report →Continue the system
Connect the adjacent layer.
Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Open guide →Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Open guide →Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.Open guide →