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Chapter 2 of 3 · Synthesis and Timing Closure

Autopsy timing paths in their physical context

Read launch, data, capture, requirements, derates, and slack, then account for placement, CTS, routing, parasitics, variation, crosstalk, and congestion.

Change the timing calculation Practice questions
Watercolor of a silicon floorplan, routing traces, a probe, and an inspection loupe.
03

Reconcile every picosecond

Autopsy the path before prescribing the ECO.

A timing report is a causal chain: launch edge, data arrival, capture edge, requirement, adjustments, and verdict.
report_timing -delay_type maxfunc_ss_cmax · group core_clk
clock core_clk (rise edge)Increment (ns)0.000Cumulative arrival (ns)0.000
clock network delay (propagated)Increment (ns)+0.100Cumulative arrival (ns)0.100
req_q[0]/CK → QIncrement (ns)+0.090Cumulative arrival (ns)0.190
AOI21_X2 / MUX2_X1 × 4Increment (ns)+0.420Cumulative arrival (ns)0.610
net RC + coupling deltaIncrement (ns)+0.450Cumulative arrival (ns)1.060
next edge + capture clock latencyEdge + latency (ns)0.850 + 0.140Capture time (ns)0.990
library setup + uncertaintySetup + uncertainty (ns)−0.110Required time (ns)0.880
slack (VIOLATED)Slack (ns)−0.180

Selected timing report region: Data path. Separate cell arcs from nets before choosing a repair.

Setup + hold edge lab

Change one term and watch both timing contracts move.

Setup slackT + (Lcap − Llaunch) − (tCQmax + tPDmax + tsetup + Usetup)−0.180 ns
Hold slacktCQmin + tCDmin − ((Lcap − Llaunch) + thold + Uhold)+0.040 ns
CLK · launch → next capturePeriod +0.850 ns · skew +0.040 ns
D max · latest arrival
+0.960 ns
Setup boundary
+0.780 ns
Setup slack
−0.180 ns
D min · earliest arrival
+0.130 ns
Hold boundary
+0.090 ns
Hold slack
+0.040 ns

Latest data must arrive before the setup boundary. Earliest new data must arrive after the same-edge hold boundary.

CLKD maxD minnext capturesetup boundaryhold boundary
latest / earliest datasetup aperturehold requirementcapture edge

Clock relationship

Skew Lcap − Llaunch+0.040 ns

Maximum path · setup

Minimum path · hold

Positive capture skew helps setup but hurts hold.In this convention, increasing Lcap − Llaunch adds setup margin and subtracts the same first-order amount from hold margin.

04

Estimates become geometry

Placement, CTS, extraction, SI, and OCV change what the path means.

Compare stages using the same endpoints so model improvements are not mistaken for design regressions.
SRAM A
SRAM B
FFL
FFC
congestion channel
coupled aggressor

Selected implementation stage: Extracted signoff. Extracted resistance, capacitance, crosstalk delta delay, slew degradation, and signoff variation decide the final path.

Pre-physical

Use estimates to expose architectural risk early.

  • Logic depth, fanout, macro choice, and target frequency
  • Wire-load or placement-independent net estimates
  • Ideal or estimated clocks
  • Coarse variation and congestion prediction
placementclock treeextracted RCSI + OCV
Post-route signoff

Use extracted evidence to make the final verdict.

  • Actual cell locations, legal routes, and pin access
  • Propagated clock latency, skew, and reconvergence
  • Coupled resistance/capacitance and slew
  • AOCV/POCV, crosstalk, CPPR, and MMMC views

Check your understanding

Questions to reason through.

Why can positive capture skew help setup but hurt hold?

A later capture clock gives the maximum-delay path more time before the next capture edge, increasing setup margin. The same later edge makes it easier for the earliest new data to reach the destination too soon relative to that capture event, reducing hold margin. Useful skew is therefore a coupled optimization, not free setup slack.

Why is a clean pre-route timing report not final evidence?

Before placement and routing, net delays, congestion, coupling, and clock-tree latency are estimated. Signoff uses extracted interconnect, propagated clocks, variation and uncertainty models, and the required mode/corner combinations. Early timing is valuable for direction, but only the implemented timing model represents the final physical path.

Put it into practice

Explain the decision behind the design.

Practice Synthesis and Timing Closure in the question bank

Continue the learning path

Next: Closure and signoff

Connect the adjacent layer

Continue across ASIC Design.