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Part 2 · Path analysis and physical reality

Autopsy timing paths in their physical context

Read launch, data, capture, requirements, derates, and slack, then account for placement, CTS, routing, parasitics, variation, crosstalk, and congestion.

Read timing evidence instead of chasing summary numbers, distinguish constraint bugs from real path failures, and choose repairs that preserve function while improving total QoR.

Updated July 20262 connected chaptersInteractive labs + worked examples
03

Reconcile every picosecond

Autopsy the path before prescribing the ECO.

A timing report is a causal chain: launch edge, data arrival, capture edge, requirement, adjustments, and verdict.
report_timing -delay_type maxfunc_ss_cmax · group core_clk
clock core_clk (rise edge)0.0000.000
clock network delay (propagated)+0.1000.100
req_q[0]/CK → Q+0.0900.190
AOI21_X2 / MUX2_X1 × 4+0.4200.610
net RC + coupling delta+0.4501.060
next edge + capture clock latency0.850 + 0.1400.990
library setup + uncertainty−0.1100.880
slack (VIOLATED)−0.180

Selected timing report region: Data path. Separate cell arcs from nets before choosing a repair.

Setup + hold edge lab

Change one term and watch both timing contracts move.

Setup slackT + (Lcap − Llaunch) − (tCQmax + tPDmax + tsetup + Usetup)−0.180 ns
Hold slacktCQmin + tCDmin − ((Lcap − Llaunch) + thold + Uhold)+0.040 ns
CLKD maxD minnext capturesetup boundaryhold boundary
latest / earliest datasetup aperturehold requirementcapture edge

Clock relationship

Skew Lcap − Llaunch+0.040 ns

Maximum path · setup

Minimum path · hold

Positive capture skew helps setup but hurts hold.In this convention, increasing Lcap − Llaunch adds setup margin and subtracts the same first-order amount from hold margin.

04

Estimates become geometry

Placement, CTS, extraction, SI, and OCV change what the path means.

Compare stages using the same endpoints so model improvements are not mistaken for design regressions.
SRAM A
SRAM B
FFL
FFC
congestion channel
coupled aggressor

Selected implementation stage: Extracted signoff. Extracted resistance, capacitance, crosstalk delta delay, slew degradation, and signoff variation decide the final path.

Pre-physical

Use estimates to expose architectural risk early.

  • Logic depth, fanout, macro choice, and target frequency
  • Wire-load or placement-independent net estimates
  • Ideal or estimated clocks
  • Coarse variation and congestion prediction
placementclock treeextracted RCSI + OCV
Post-route signoff

Use extracted evidence to make the final verdict.

  • Actual cell locations, legal routes, and pin access
  • Propagated clock latency, skew, and reconvergence
  • Coupled resistance/capacitance and slew
  • AOCV/POCV, crosstalk, CPPR, and MMMC views

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.
01Why can positive capture skew help setup but hurt hold?

A later capture clock gives the maximum-delay path more time before the next capture edge, increasing setup margin. The same later edge makes it easier for the earliest new data to reach the destination too soon relative to that capture event, reducing hold margin. Useful skew is therefore a coupled optimization, not free setup slack.

02Why is a clean pre-route timing report not final evidence?

Before placement and routing, net delays, congestion, coupling, and clock-tree latency are estimated. Signoff uses extracted interconnect, propagated clocks, variation and uncertainty models, and the required mode/corner combinations. Early timing is valuable for direction, but only the implemented timing model represents the final physical path.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.
Calculate maximum frequencyUse a setup path with skew and uncertainty correctly.Reason about capture skewTrack opposite effects on setup and hold.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.