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Computer Architecture · Foundations
Follow one instruction from its software-visible contract through the datapath, cache hierarchy, address translation, and physical memory.
4 chapters · One learning path
Each chapter has a worked explanation and an experiment. Start at chapter 1, or jump to the problem in front of you.
Put it into practice
Choose a prompt, or follow the chapters to build the model behind it.
One instruction, every layer
The trace assumes a 4 KiB page, 32 KiB 8-way VIPT L1, 64-byte lines, and a 40-bit physical address. The set read begins with page-offset bits while translation proceeds. Candidate data remains unusable until the physical tag and permissions arrive.
Latency note: a cold four-level walk plus DRAM refill can cost hundreds of cycles. Exact latency depends on cached PTEs, lower-level hits, memory-level parallelism, and the machine's miss machinery.
Check your understanding
In the scalar five-stage pipeline shown here, a load produces its value at the end of the memory stage, while the next instruction needs that operand at the start of execute. With the stated bypass timing, the dependent instruction stalls for one cycle. Other pipeline organizations and memory latencies can require different handling.
Associativity gives every index multiple candidate lines. Addresses with the same index can coexist in different ways instead of repeatedly evicting one another, at the cost of more tag comparisons, replacement state, power, and often hit latency.
The processor or operating system walks the page-table hierarchy using the virtual-page number. A valid leaf supplies the physical-page number and permissions, the translation is installed in the TLB, and the original access restarts. An invalid or disallowed entry raises a page fault or protection exception.
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