Instructions to memory

Computer Organization

Follow one instruction from its software-visible contract through the datapath, cache hierarchy, address translation, and physical memory.

Reason cycle by cycle, calculate the cost of misses and stalls, and explain why each implementation choice changes performance or correctness.

Updated July 20266 connected chaptersInteractive labs + worked examples

Part 1 · Instruction pipeline

ISA, datapath, pipeline, and hazards

Connect the software-visible instruction contract to the five-stage datapath, then locate structural, data, and control hazards cycle by cycle.

Start Part 1

Part 2 · Cache hierarchy

Cache mapping, misses, VIPT, and MSHRs

Decompose addresses, compare associativity and write policies, classify miss causes, and reason about VIPT and non-blocking cache structures.

Open Part 2

Part 3 · Virtual memory

TLBs, page walks, protection, and huge pages

Follow a virtual address through translation and protection, then reason about TLB misses, shootdowns, page-table state, and page-size tradeoffs.

Open Part 3

Part 4 · Performance labs

CPI, MIPS, AMAT, storage, and EMAT

Work the quantitative problems with explicit hit-rate denominators, timing assumptions, units, and reproducible intermediate steps.

Open Part 4

Practice with real interview promptsPractice Computer Organization in the question bank

One instruction, every layer

Trace a load from opcode to physical data.

Cold-path lensTLB miss + L1 miss

ISSUE: LW x5,24(x2)
BASE: x2 = 0x00008130
VA: 0x00008148
VPN / OFFSET: 0x8 / 0x148
L1 SET / BYTE: 05 / 08
PPN: 0x1A3
PA: 0x001A3148
REFILL LINE: 0x001A3140

Core · cycles 1–4

ISA contractLW x5,24(x2)load 32-bit wordC1 · IFFetch instructionPC advancesC2 · IDRead x2, name x5sign-extend 24C3 · EX0x8130 + 24VA = 0x8148C4 · MEMStart lookuppipeline waits on miss

MEM · parallel lookup

Translation pathVirtual addressVPN 0x84 KiB pageTLB lookupMissno cached mappingFour-level walkL4 → L3 → L2 → L1leaf PTE permits readTranslationPPN 0x1A3PA 0x001A3148

VIPT SRAM pathPage-offset bitsindex 05 · byte 08unchanged by translationL1 set readRead 8 waystags + 64 B linesCandidate stateHold way outputsphysical tag not readyTag compareNo valid matchL1 miss

Resolve · refill · WB

Physical tag0x1A3permission checkedL2 / L3Cold missrequest continuesPhysical memoryRead line 0x001A314064-byte refillInstallSet 05 · chosen wayvalid tag 0x1A3WB after refillword at line + 8 → x5instruction completes

The trace assumes a 4 KiB page, 32 KiB 8-way VIPT L1, 64-byte lines, and a 40-bit physical address. The set read begins with page-offset bits while translation proceeds. Candidate data remains unusable until the physical tag and permissions arrive.

Latency note: a cold four-level walk plus DRAM refill can cost hundreds of cycles. Exact latency depends on cached PTEs, lower-level hits, memory-level parallelism, and the machine's miss machinery.

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.

01Why can forwarding not completely remove a load-use hazard?

A load produces its value only after the memory stage, while the immediately following instruction needs that operand at the start of execute. Even a direct MEM-to-EX bypass arrives too late for the same cycle, so the dependent instruction stalls for one cycle.

02How does associativity reduce conflict misses?

Associativity gives every index multiple candidate lines. Addresses with the same index can coexist in different ways instead of repeatedly evicting one another, at the cost of more tag comparisons, replacement state, power, and often hit latency.

03What happens on a TLB miss?

The processor or operating system walks the page-table hierarchy using the virtual-page number. A valid leaf supplies the physical-page number and permissions, the translation is installed in the TLB, and the original access restarts. An invalid or disallowed entry raises a page fault or protection exception.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Pipeline dependency streamGenerate instructions while respecting temporal hazards.Exact LRU cache controlReason about tags, ways, and replacement state.Memory Systems questionsContinue with cache, TLB, DRAM, and coherency scenarios.

Continue the system

Connect the adjacent layer.

Parallel work to precise stateComputer ArchitectureSee how a modern processor finds parallel work, predicts control flow, executes speculatively, and still presents precise sequential behavior.