Part 1 · Synthesis and constraints

Map RTL and define the timing problem

Follow elaboration, inference, optimization, and technology mapping, then constrain clocks, I/O, uncertainty, relationships, modes, corners, and legitimate exceptions.

Read timing evidence instead of chasing summary numbers, distinguish constraint bugs from real path failures, and choose repairs that preserve function while improving total QoR.

Updated July 20262 connected chaptersInteractive labs + worked examples

RTL intent becomes timed structure

Synthesis is inference followed by legal, library-aware optimization.

Read the mapped structure as the tool’s interpretation of the RTL, not as an inevitable implementation.

issue_select.svElaborated RTL

always_comb begin
  next = hold;
  for(int i = 0; i < 4; i++)
    if(req[i] && !busy[i])
      next = payload[i];
end

The loop is priority logic. The final assignment wins, so elaboration creates a serial select cone unless the intent or coding structure changes.

01Elaborateparameters + generates

Resolve hierarchy, widths, constant conditions, and signedness.

02Inferflops · muxes · arithmetic

Recognize state, enables, comparators, adders, and memories.

03OptimizeBoolean + sequential

Propagate constants, share or duplicate logic, and retime when legal.

04Maplibrary cells

Choose real arcs, drive strengths, Vt flavors, and legal macros.

Mapped cone4 priority MUX2 stages · highest index wins

Mapped cell delay0.38 nsEstimated net0.11 nsFirst questionIs the serial priority intentional?

State inference

Every register, latch, and memory must be intentional.

Review inferred clocks, enables, resets, RAM modes, latch reports, width truncation, signed operations, and combinational loops before timing optimization hides the original symptom.

Optimization boundary

Preserve observability only where the architecture needs it.

Hierarchy, dont-touch directives, test structures, and debug visibility can block duplication, retiming, and constant propagation. Each preservation constraint spends QoR.

Evidence

Compare RTL intent, mapped topology, and equivalence.

Lint and elaboration explain the source. Synthesis reports explain the structure. Formal or logical equivalence proves that legal transformations preserve the defined behavior.

Completeness before optimization

A timing graph is only as trustworthy as its clocks and path intent.

Treat constraints as an executable interface specification with coverage, ownership, and review evidence.

Selected constraint group: Clock roots. Does every sequential endpoint inherit the intended waveform?

Constraint ledgerClock roots

Question the SDC must answer

Does every sequential endpoint inherit the intended waveform?

create_clockcreate_generated_clockset_clock_latencyset_clock_uncertainty

Evidence: List all clocks, their sources, periods, waveforms, generated-clock masters, and propagated status.
Failure if absent or broad: A missing generated clock can time logic against the wrong edge or leave a domain unconstrained.

Pre-closure gate

Do not optimize until the report universe is complete.

Coverage areaRelease conditionEvidence to inspect

Clock coverage0 unconstrained sequential endpointsReport all clock pins and no-clock checks

I/O coverageEvery legal port has min and max budgetsReconcile against the system timing budget

Interaction matrixEvery clock pair classifiedSynchronous, asynchronous, or exclusive with rationale

ExceptionsApplied, scoped, and independently justifiedReview ignored and overridden exceptions

ModesEvery case-analysis branch ownedProve disabled arcs and test controls are intentional

Path sanityTop paths match architectureSample startpoints, endpoints, and edge pairing

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Explain what STA provesSeparate timing-graph evidence from functional behavior.Classify path boundariesIdentify legal startpoints, endpoints, and clock relationships.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.