Logic to reliable timing
Connect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.
Diagnose whether a failure comes from function, timing, constraints, or clock-domain assumptions and select a repair that remains safe in silicon.
One signal · four design contracts
Y = (A XOR B) AND EN = 1Open logic chapter ↘02 · Launch and transportFF_A launches one timed value.Only FF2 fans into destination logic. The structure reduces escape probability; it does not prevent FF1 metastability.
Choose a CDC structure ↘Logic and state
Digital logic becomes easier to reason about when every block has an explicit contract: transform current inputs, or sample and retain state. Timing then tells us whether that contract is physically achievable.
y(t) = f(x(t))Output depends only on current inputs. There is no intentional state or sampling edge.
Q(next) = f(Q(now), x)State changes at a defined event, normally a clock edge. Past history is represented by stored state.
Truth table, equation, state diagram, or cycle-level contract.
Combinational network plus the minimum intentional state.
Maximum delay for setup, minimum delay for hold, and CDC intent.
Simulation, assertions, lint, STA, CDC, and implementation checks.
Setup, hold, and register paths
Setup checks the latest arriving data before capture. Hold checks the earliest changing data after capture. They use different delay corners and require different fixes.
The minimum interval that D must be stable before the active capture edge. A setup failure means the maximum data path arrives after the required time.
Intuition: have the input ready before the sampling buzzer.
Tperiod + Tskew ≥ tCQ(max) + Tcomb(max) + TsetupTypical repairs: pipeline, restructure HDL, reduce logic depth, use faster cells or higher synthesis effort, improve placement, or lengthen the period as a last resort.The minimum interval that D must remain stable after the active capture edge. A hold failure means the minimum data path changes too early.
Intuition: keep the input still just after the sampling buzzer.
tCQ(min) + Tcomb(min) ≥ Thold + TskewTypical repairs: insert minimum-delay cells, detour routing, or reduce harmful skew. Frequency reduction does not help.Register timing boundaries
Interactive waveform
Data is stable on both sides of the sampling edge. The transition finishes before the setup window begins. The receiving register sees one unambiguous value for the complete aperture.
Register-to-register timing lab
Positive capture skew gives the setup path more time but makes the hold requirement harder in this simplified same-clock model.
Solve arrival time first, required time second, then compute slack = required − arrival.
Live arrival versus requirement
Required 1.88 ns − arrival 1.57 ns
Maximum path meets setup.Arrival 0.18 ns − required 0.14 ns
Minimum path meets hold.Setup slack 0.31 nanoseconds, passing. Hold slack 0.04 nanoseconds, passing.
Variation-aware timing
Process, voltage, temperature, local variation, crosstalk, and clock-tree behavior move launch, data, and capture delays differently. Signoff tests pessimistic combinations, not only a nominal waveform.
Slow launch clock-to-Q and data logic compete with an early capture clock edge. Maximum delay and frequency dominate.
Fast launch clock-to-Q and a short data path compete with a late capture edge. Minimum delay and skew dominate.
AOCV or POCV adjusts delay by path depth and variation. Common-path pessimism removal avoids charging the same shared clock segment as both early and late.
Timing intent
False paths and multicycle paths change what static timing analyzes. Both need an architectural proof. They are not interchangeable fixes for a difficult implementation path.
Analyzed edge window
Path does not functionally exist
No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data.
Conceptual SDC
set_false_path -from [get_pins src_reg/Q] \
-to [get_pins dst_reg/D]Showing False path. No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data. No setup or hold capture edge is analyzed.
Reset, test, configuration, enables, and clock mode all matter.
Read the timing report after the exception, including hold.
Use assertions, formal reachability, or protocol verification.
Clock-domain crossing
Metastability is an analog consequence of sampling near an aperture. A CDC structure contains that risk and preserves the payload’s protocol: level, event, coherent value, or stream.
CDC structure selector
Recommended mechanism
The first stage may become metastable; the second gets almost a full destination period for that analog state to resolve.
The source level must remain stable long enough to be observed for at least one destination sampling opportunity.
Do not synchronize each bit of a related bus independently. Their resolving cycles can differ.
Usually two destination edges, with a possible extra cycle depending on phase. There is no acknowledgment or backpressure.
Constrain the minimum source pulse width, mark the synchronizer stages, place them close, and calculate MTBF for the real toggle and clock rates.
For Slow single-bit level, use 2-flop synchronizer. The first stage may become metastable; the second gets almost a full destination period for that analog state to resolve.
Why Gray pointers help an async FIFO
Binary 0111 → 1000 changes four bits. Gray 0100 → 1100 changes one. The synchronized pointer may be old, which is safe for conservative full/empty decisions, but it is far less likely to look like an unrelated mixed value.
Reset-domain crossing
An asynchronous reset may assert without a running clock, but its deassertion must satisfy recovery and removal. Synchronize deassertion separately in every clock domain, then exchange explicit ready or initialization state before domains interact.
Reconvergence risk
Two independently synchronized control bits can emerge on different destination cycles. Even duplicate synchronizers fed by one source may disagree temporarily. Synchronize once and fan out locally, or transfer an encoded state, bundle, handshake, or FIFO entry atomically.
CDC and RDC signoff
Lab-to-silicon debug
Both failures below look logical at first. The decisive evidence comes from clock ancestry, minimum delay, pulse width, phase behavior, and the protocol used to move state.
Decoded counter enable
The source asks why a one-cycle counter decode could fail in hardware even though RTL simulation looks deterministic.
The slide’s intended risk is a minimum-delay path from counter Q through a small equality comparator to the destination enable mux or clock-enable pin. Unequal counter-bit delays can also make the equality decode glitch as the bits reconverge.
logic [3:0] count;
wire enable = (count == 4'd15);
always_ff @(posedge clk) begin
count <= count + 1'b1;
end
always_ff @(posedge clk) begin
if (enable) data_reg <= data_in;
endThe slide is aiming at a hold or minimum-delay check on counter Q through the equality decode to the destination enable path. Setup must also be checked at the maximum-delay corner.
As written, both blocks use the same clock, so this is a normal synchronous register-to-register control path. A combinational enable is not automatically a violation. STA must decide from real min delay and skew.
Several counter bits can change with unequal delays and reconverge in the comparator. A transient is dangerous if it overlaps a sampling aperture or is misused as a clock or asynchronous control.
Compare against 14, register the result, and consume that registered enable when the old counter value is 15. Keep the root clock and verify the new path’s setup, hold, and pulse alignment.
Before: a multi-bit decode feeds a synchronous enable directly. The slide’s intended risk is a minimum-delay path from counter Q through a small equality comparator to the destination enable mux or clock-enable pin. Unequal counter-bit delays can also make the equality decode glitch as the bits reconverge.
The reusable reasoning model
Reasoning checkpoints
Setup is a maximum-delay check: old-cycle data must reach the capture register before its active edge. Hold is a minimum-delay check: new-cycle data must not reach that register too soon after the edge. Setup is helped by a longer period or faster data path; hold usually needs added data delay or improved skew.
Each bit can resolve and be sampled on a different destination cycle, producing a word that never existed in the source domain. Multi-bit transfers need a protocol that holds a coherent word, such as a handshake, Gray-coded control transfer, or asynchronous FIFO.
A false path cannot be sensitized in the defined operating modes and is excluded from timing. A multicycle path is real and must work, but the design deliberately allows more than one clock cycle. Calling a slow real path false hides a functional timing failure.
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