Logic to reliable timing

Digital Design

Connect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.

Start chapter 1 Explore 3 chapters

3 chapters · One learning path

Choose the mechanism you want to understand.

Follow the chapters in order, or open the boundary you are working on.

Chapter 1Logic and timingDecide whether behavior needs memory, then trace maximum- and minimum-delay paths through launch, transport, and the capture aperture.Open chapter 1
Chapter 2Timing intentUse timing exceptions only when the functional contract justifies a different analysis edge—or proves that no legal capture edge exists at all.Open chapter 2
Chapter 3CDC and debugMatch the payload to a safe crossing protocol, contain metastability, reason about Gray pointers and reset release, then debug failures from physical evidence.Open chapter 3

Explore the system

Explore the timing path

One signal · four design contracts

Follow a bit from Boolean intent to safe state.

Inputs form a combinational result, a launch register samples it, the data path meets a capture aperture, and a synchronizer contains metastability before another clock domain consumes it.

Logic: Y = 1
Setup: +0.31 ns
Hold: +0.04 ns
CDC: 2FF level

CLK launches data → D travels → capture aperture

tCQ begins at launch. D must settle before SETUP and stay stable through HOLD. An async event arrives independently of the receiving clock.

01 · Boolean intentInputs enter a combinational cone.

A1B0EN1

Y = (A XOR B) AND EN = 1Open logic chapter ↘02 · Launch and transportFF_A launches one timed value.

DFF_AQ

tCQ max: 0.12 ns
logic + route: 1.45 ns
arrival: 1.57 ns

Open timing lab ↘03 · Capture contractFF_B owns the sampling aperture.

stable before↑ edgestable after

required: 1.88 ns
setup slack: +0.31 ns
hold slack: +0.04 ns

Review edge exceptions ↘04 · CDC containmentA new domain samples persistent state.

async levelFF1may resolveFF2clean output

Only FF2 fans into destination logic. The structure reduces escape probability; it does not prevent FF1 metastability.

Choose a CDC structure ↘

The design contract changes at every boundary.Boolean correctness, maximum and minimum delay, exception intent, and CDC protocol each require different evidence.

Put it into practice

Explain the decision behind the design.

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Digital Design

Choose the mechanism you want to understand.

Explore the timing path

Follow a bit from Boolean intent to safe state.

Explain the decision behind the design.

Continue across ASIC Design.

Digital Design

Choose the mechanism you want to understand.

Explore the timing path

Follow a bit from Boolean intent to safe state.

Explain the decision behind the design.

Continue across ASIC Design.