Logic to reliable timing

Digital Design

Connect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.

Diagnose whether a failure comes from function, timing, constraints, or clock-domain assumptions and select a repair that remains safe in silicon.

Updated July 20265 connected chaptersInteractive labs + worked examples

Part 1 · Logic and timing

Logic, state, setup, hold, and register paths

Decide whether behavior needs memory, then trace maximum- and minimum-delay paths through launch, transport, and the capture aperture.

Start Part 1

Part 2 · Timing intent

False paths, multicycle paths, and proof obligations

Use timing exceptions only when the functional contract justifies a different analysis edge—or proves that no legal capture edge exists at all.

Open Part 2

Part 3 · CDC and debug

CDC containment and lab-to-silicon debug

Match the payload to a safe crossing protocol, contain metastability, reason about Gray pointers and reset release, then debug failures from physical evidence.

Open Part 3

Practice with real interview promptsPractice Digital Design in the question bank

One signal · four design contracts

Follow a bit from Boolean intent to safe state.

Inputs form a combinational result, a launch register samples it, the data path meets a capture aperture, and a synchronizer contains metastability before another clock domain consumes it.

Logic: Y = 1
Setup: +0.31 ns
Hold: +0.04 ns
CDC: 2FF level

01 · Boolean intentInputs enter a combinational cone.

A1B0EN1

Y = (A XOR B) AND EN = 1Open logic chapter ↘02 · Launch and transportFF_A launches one timed value.

DFF_AQ

tCQ max: 0.12 ns
logic + route: 1.45 ns
arrival: 1.57 ns

Open timing lab ↘03 · Capture contractFF_B owns the sampling aperture.

stable before↑ edgestable after

required: 1.88 ns
setup slack: +0.31 ns
hold slack: +0.04 ns

Review edge exceptions ↘04 · CDC containmentA new domain samples persistent state.

async levelFF1may resolveFF2clean output

Only FF2 fans into destination logic. The structure reduces escape probability; it does not prevent FF1 metastability.

Choose a CDC structure ↘

The design contract changes at every boundary.Boolean correctness, maximum and minimum delay, exception intent, and CDC protocol each require different evidence.

Continue the system

Connect the adjacent layer.

Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.