Chapter 3 of 3 · Synthesis and Timing Closure

Choose coupled ECOs and close every signoff view

Select architectural, logical, sizing, placement, routing, and skew repairs while protecting hold, power, area, equivalence, test modes, and MMMC signoff.

Compare timing repairs Practice questions

Repair the mechanism, not the symptom

Every timing ECO moves setup, hold, power, area, and risk.

Choose the highest-leverage layer that can still change, then remeasure the whole affected timing neighborhood.

Setup-slack waterfallRestructure logic

Baseline−0.180 ns

ECO contribution+0.190 ns

Reanalyzed+0.010 ns

Selected repair: Restructure logic. Setup change +0.190 ns; hold change −0.010 ns.

Setup+0.190 ns

Hold−0.010 ns

Power↔ or ↓ activity

Areadepends on sharing

1Constraint

Prove the path and analysis view are real.

2Architecture

Pipeline, parallelize, or change the protocol while flexibility remains.

3Logic

Restructure depth, fanout, arithmetic, and sharing.

4Physical

Place, buffer, route, size, and tune Vt with local evidence.

5Clock + min delay

Use skew and hold ECOs only with coupled-view checks.

6Re-signoff

Repeat MMMC, noise, power, DRC, and equivalence evidence.

MMMC evidence and release discipline

Signoff means every legal scenario closes without breaking equivalence or PPA.

One green corner is not a tapeout decision. Build a reviewable matrix of modes, libraries, RC corners, checks, and owners.

Selected analysis view: Functional, Setup, WNS −0.18 ns.

Beyond register-to-register data

Four edge contracts still need dedicated signoff views.

01Recovery

Reset deassertion must settle before the active edge. Treat it like a setup-style maximum-delay check.

02Removal

Reset deassertion must not change too soon after the active edge. Treat it like a hold-style minimum-delay check.

03Pulse width

High and low clock phases must each exceed the library minimum after propagated-tree distortion.

04Gating check

The enable must remain stable across the clock-gate latch aperture so no runt pulse reaches the tree.

Release evidence

Close the design, not only the setup table.

Timing

All setup, hold, recovery/removal, pulse-width, and gated-clock checks close in every required view.

Constraints

No unintended unconstrained endpoints; clocks, exceptions, case analysis, and scenario bindings are reviewed.

SI + variation

Crosstalk, extracted RC, derates, CPPR, noise, and variation models match the signoff methodology.

Equivalence

RTL-to-synthesis and post-ECO logical equivalence pass with intentional transforms explicitly handled.

Physical

DRC, LVS, antenna, density, electromigration, IR drop, and clock checks satisfy release criteria.

PPA

Frequency closure does not exceed dynamic power, leakage, area, congestion, or reliability budgets.

Test + low power

Scan, at-speed test, isolation, retention, reset, and power-state timing views remain legal.

Reproducibility

Tool versions, libraries, corners, constraints, waivers, reports, and checksums are archived.

Primary references

Constraint and closure methodology

These AMD references are FPGA-oriented, but their disciplined treatment of clocks, exceptions, path coverage, methodology checks, and closure baselines transfers directly to ASIC timing reasoning. ASIC signoff additionally depends on foundry libraries, extracted parasitics, variation, SI, IR/EM, and physical-verification flows; OpenSTA provides an ASIC-oriented, inspectable reference implementation for Liberty, SDC, SPEF, SDF, and gate-level timing analysis.

AMD UG903Using ConstraintsClocks, I/O delays, exceptions, and constraint scoping ↗AMD UG949UltraFast Design MethodologyBaseline, methodology checks, QoR, and design closure ↗OpenROAD projectOpenSTA timing engineLiberty, SDC, SPEF, SDF, corners, and gate-level STA ↗

Check your understanding

Questions to reason through.

What should you check before fixing negative slack?

Verify the clocks and generated clocks, modes, I/O delays, uncertainty, exceptions, case analysis, path grouping, and whether the reported startpoint and endpoint match architectural intent. Then inspect the full path and physical context. Optimizing a path created by a bad constraint wastes effort; cutting a real failing path hides a bug.

Put it into practice

Explain the decision behind the design.

Practice Synthesis and Timing Closure in the question bank

Complete the guide

Apply the model to a real question.

Connect the adjacent layer