Safe boundaries across time and voltage

Clock, Reset, CDC and Power

Operate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.

Classify each boundary by clock relationship, payload semantics, reset behavior, and power state; then select a structure and signoff evidence that remain safe in silicon.

Updated July 20266 connected chaptersInteractive labs + worked examples

Part 1 · Domains and reset

Map domains and release reset safely

Record clock provenance, reset ownership, voltage, traffic, and state, then prove asynchronous assertion, local release, recovery, removal, and reset-domain crossings.

Start Part 1

Part 2 · CDC and clocks

Select CDC protocols and constrain real clock relationships

Match levels, events, bundles, and streams to safe crossings, quantify metastability risk, preserve Gray-pointer assumptions, and gate clocks without glitches.

Open Part 2

Part 3 · Power and sequencing

Express power intent and prove sleep and wake sequencing

Coordinate level shifting, isolation, retention, power switches, clocks, reset, and software-visible readiness across safe power-down and restoration.

Open Part 3

Practice with real interview promptsPractice Clock, Reset, CDC and Power in the question bank

Boundary control room · active

One island. Three clocks. Four meanings.

The same pair of domains needs different circuitry for a persistent mode, a short event, a coherent configuration word, and a continuous sample stream.

Power stateACTIVEPLL lockLOCKEDIsolationOPENOutstanding03 samples

PD_AON · 0.80 V

Always-on control

Clock: clk_aon · 50 MHz
Reset: por_n → rst_aon_n
Power: Always on

PD_SENSOR · 1.00 V

Sensor peripheral

Clock: clk_sensor · 125 MHz
Reset: rst_sensor_n
Power: Standby capable

Boundary fabricSynchronizers · handshake · async FIFOIsolation + level shifting at PD_COMPUTE boundary

PD_COMPUTE · 0.72 V

Compute island

Clock: clk_compute · PLL 500 MHz
Reset: rst_compute_n
Power: Switchable + retention

Always-on power managerQuiesce → isolate → gate → switchOwns wake dependencies and domain-ready

Sensor peripheralCompute island

UseAsynchronous FIFO

ContractDual-port storage keeps data local; only Gray pointers cross.

DeliveryElastic

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.