Part 1 · Domains and reset

Map domains and release reset safely

Record clock provenance, reset ownership, voltage, traffic, and state, then prove asynchronous assertion, local release, recovery, removal, and reset-domain crossings.

Classify each boundary by clock relationship, payload semantics, reset behavior, and power state; then select a structure and signoff evidence that remain safe in silicon.

Updated July 20262 connected chaptersInteractive labs + worked examples

Domain atlas

Draw the boundaries before choosing circuitry.

Start with clock provenance, reset ownership, voltage, switchability, and payload direction. Frequency alone never tells you whether a crossing is synchronous.

Primary sourceCrystalIndependent sourceSensor clockElectrical + temporal boundaryCDC · RDC · isolation · level shift

Switchable consumer

Compute island

Clock: clk_compute · 500 MHz
Provenance: PLL output behind an ICG
Reset: Local release after power-good + PLL lock
Power: 0.72 V · Switchable, selected state retained
Traffic: Configuration, samples, completion
Owned state: Filter pipeline, FIFO read side, retained mode
Signoff boundary: CDC + RDC + power-aware + clock-gating checks

Boundary ledger: every crossing receives four classifications
Payload	Source → destination	Clock relation	Reset epoch	Power rule
mode_en	AON → compute	Related while compute clock runs	AON survives compute reset	Clamp before compute OFF
sample_event	Sensor → AON	Independent clocks	Reject stale toggle epoch	Both domains powered
config[31:0]	AON → compute	Related bundled transfer	Handshake restarts after reset	Level shift + isolation
samples	Sensor → compute	Dual-clock FIFO	Pointers converge from empty	Drain before compute OFF

Reset and RDC

Release locally. Reconnect deliberately.

Asynchronous assertion can force safety without a clock. Deassertion is a timed local event, and related state must not reconverge until reset epochs agree.

RDC release scopeSafe structure

Each domain releases reset on its own active edges.Power-good and PLL lock qualify the asynchronous request. A two-stage local chain then deasserts reset in each domain; traffic waits for synchronized domain-ready.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Design reset releaseUse asynchronous assertion and local synchronous deassertion.Monitor reset sequencingCheck cross-domain initialization and dependency order.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.