Part 3 · Power and sequencing

Express power intent and prove sleep and wake sequencing

Coordinate level shifting, isolation, retention, power switches, clocks, reset, and software-visible readiness across safe power-down and restoration.

Classify each boundary by clock relationship, payload semantics, reset behavior, and power state; then select a structure and signoff evidence that remain safe in silicon.

Updated July 20262 connected chaptersInteractive labs + worked examples

Power intent

Keep electrical truth beside functional intent.

RTL describes logic behavior. IEEE 1801 UPF adds supply networks, power domains, switch control, isolation, retention, level shifting, and legal power states.

UPF-aware topologyPD_COMPUTE is switchable; PD_AON owns safety.

VDD_AON · 0.80 VVDD_SENSOR · 1.00 VVDD_COMPUTE · 0.72 V

PD_AONPower managerAlways-on control + isolation enable

LSLevel shifterISOClamp compute outputs

PD_COMPUTEFilter pipelinePower switch + retained mode register

Retention supplymode_reg · calibration_epochSave before switch-off · restore before reconnect

Legal compute-island states
State	Supply	Clock	Isolation	Retention	Traffic
ACTIVE	ON	RUN	OPEN	TRACK	LEGAL
IDLE	ON	GATED	OPEN	TRACK	BLOCKED
RETENTION	RET	OFF	CLAMP	SAVED	BLOCKED
OFF	OFF	OFF	CLAMP	SELECTED HOLD	BLOCKED

IsolationClamp outputs from a domain that may be off before its supply becomes invalid. Choose clamp values from the receiving protocol's safe state.

Level shiftingInsert direction-appropriate cells when voltage domains differ. Cell placement and supply ownership are implementation decisions encoded by power intent.

RetentionRetain only state whose restoration cost justifies the always-on leakage and sequencing complexity. Reset and retained state need an explicit precedence rule. This worked subsystem holds mode_reg and calibration_epoch in OFF; a cold-off policy may discard them only if wake skips restore and reinitializes that state instead.

Safe sleep and wake

Quiesce first. Reconnect last.

Power transitions are distributed protocols. Every step has an owner, prerequisite, acknowledgment, timeout, and proof that accepted work is not lost.

Step 01 of 10

Compute accepts samples and may create new work.

SupplyONClockRUNResetRELEASEDIsolationOPENRetentionTRACKTrafficACCEPTOutstanding3

Why nowAll dependencies are valid: supply, PLL, clock, reset, isolation, and domain-ready.

Prove itTraffic is legal only while domain_ready is true.

Architecture contractRTL + UPFSTA · CDC · RDCPower-aware simulationAssertions + formalImplementation signoff

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.

01What is the safe order for powering down a domain?

Stop new work, drain or cancel accepted work according to the protocol, save retained state, assert isolation while source outputs are still valid, gate clocks when the domain is idle, then remove power. Wake-up reverses the dependency carefully: restore power, wait for stability, enable clocks, restore or reset state, validate readiness, and only then release isolation and accept traffic.

Keep practicing

Move from recognition to explanation.

These links open the existing practice bank without publishing protected solutions on this guide.

Sequence low-power controlsCoordinate retention, isolation, switching, and restore.

Continue the system

Connect the adjacent layer.

Logic to reliable timingDigital DesignConnect logic behavior to its physical timing contract, then choose safe structures for paths that cross cycles, clocks, and module boundaries.Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.