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Chapter 3 of 3 · Clock, Reset, CDC and Power

Express power intent and prove sleep and wake sequencing

Coordinate level shifting, isolation, retention, power switches, clocks, reset, and software-visible readiness across safe power-down and restoration.

Step through sleep and wake Practice questions
Watercolor of two clock domains joined by a small bridge of register blocks.
05

Power intent

Keep electrical truth beside functional intent.

RTL describes logic behavior. IEEE 1801 UPF adds supply networks, power domains, switch control, isolation, retention, level shifting, and legal power states.

UPF-aware topologyPD_COMPUTE is switchable; PD_AON owns safety.
VDD_AON · 0.80 VVDD_SENSOR · 1.00 VVDD_COMPUTE · 0.72 V
PD_AONPower managerAlways-on control + isolation enable
LSLevel shifterISOClamp compute outputs
PD_COMPUTEFilter pipelinePower switch + retained mode register
Retention supplymode_reg · calibration_epochSave before switch-off · restore before reconnect
Legal compute-island states
StateSupplyClockIsolationRetentionTraffic
ACTIVEONRUNOPENTRACKLEGAL
IDLEONGATEDOPENTRACKBLOCKED
RETENTIONRETOFFCLAMPSAVEDBLOCKED
OFFOFFOFFCLAMPSELECTED HOLDBLOCKED

IsolationClamp outputs from a domain that may be off before its supply becomes invalid. Choose clamp values from the receiving protocol's safe state.

Level shiftingInsert direction-appropriate cells when voltage domains differ. Cell placement and supply ownership are implementation decisions encoded by power intent.

RetentionRetain only state whose restoration cost justifies the always-on leakage and sequencing complexity. Reset and retained state need an explicit precedence rule. This worked subsystem holds mode_reg and calibration_epoch in OFF; a cold-off policy may discard them only if wake skips restore and reinitializes that state instead.

06

Safe sleep and wake

Quiesce first. Reconnect last.

Power transitions are distributed protocols. Every step has an owner, prerequisite, acknowledgment, timeout, and proof that accepted work is not lost.

Step 01 of 10

Compute accepts samples and may create new work.

SupplyONClockRUNResetRELEASEDIsolationOPENRetentionTRACKTrafficACCEPTOutstanding3

Why nowAll dependencies are valid: supply, PLL, clock, reset, isolation, and domain-ready.

Prove itTraffic is legal only while domain_ready is true.

Architecture contractRTL + UPFSTA · CDC · RDCPower-aware simulationAssertions + formalImplementation signoff

Check your understanding

Questions to reason through.

What is the safe order for powering down a domain?

Stop new work, drain or cancel accepted work according to the protocol, save retained state, assert isolation while source outputs are still valid, gate clocks when the domain is idle, then remove power. Wake-up reverses the dependency carefully: restore power, wait for stability, enable clocks, restore or reset state, validate readiness, and only then release isolation and accept traffic.

Put it into practice

Explain the decision behind the design.

Practice Clock, Reset, CDC and Power in the question bank

Complete the guide

Apply the model to a real question.

Connect the adjacent layer

Continue across ASIC Design.