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Chapter 2 of 3 · Digital Design

False paths, multicycle paths, and proof obligations

Use timing exceptions only when the functional contract justifies a different analysis edge—or proves that no legal capture edge exists at all.

Compare timing exceptions Practice questions
Watercolor of an engineer’s notebook connecting a block diagram to a silicon package.

Timing intent

An exception must describe function, not discomfort.

False paths and multicycle paths change what static timing analyzes. Both need an architectural proof. They are not interchangeable fixes for a difficult implementation path.

Analyzed edge window

No launch-to-capture timing check remains.

analysis disabled
  1. C0 · launch edgeThe structural path may exist, but no legal mode sensitizes it.
  2. ↓ C1 · default captureset_false_path removes both setup and hold analysis.
  3. ↓ C2 · second captureEvery candidate edge needs functional justification for removal.
  4. ↓ C3 · later edgeNo additional capture change is implied.
False path analyzed clock edgesThe path may exist structurally, but both setup and hold analysis are disabled, so no candidate capture edge is timed.C0C1C2C3SETUPHOLDlaunchset_false_path removes setup analysisset_false_path removes hold analysisFunctional proof must justify removing every candidate edge.
False does not mean slow. It means no legal mode can sensitize the path, so neither setup nor hold has a meaningful capture edge.

Path does not functionally exist

False path

No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data.

Setup
Removed from setup analysis
Hold
Removed from hold analysis
Proof obligation
Prove the mutual exclusion, test mode, reset state, or configuration invariant that makes the path unreachable.
Source example
A test-mode and functional-mode mux pair whose select conditions are mutually exclusive, so no legal state can sensitize the complete path.

Conceptual SDC

set_false_path -from [get_pins src_reg/Q] \
  -to [get_pins dst_reg/D]

Showing False path. No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data. No setup or hold capture edge is analyzed.

01

Name the functional mode.

Reset, test, configuration, enables, and clock mode all matter.

02

Inspect the actual edges.

Read the timing report after the exception, including hold.

03

Prove the assumption.

Use assertions, formal reachability, or protocol verification.

Check your understanding

Questions to reason through.

How is a false path different from a multicycle path?

A false path cannot be sensitized in the defined operating modes and is excluded from timing. A multicycle path is real and must work, but the design deliberately allows more than one clock cycle. Calling a slow real path false hides a functional timing failure.

Put it into practice

Explain the decision behind the design.

Practice Digital Design in the question bank

Continue the learning path

Next: CDC and debug

Connect the adjacent layer

Continue across ASIC Design.