Part 2 · Timing intent

False paths, multicycle paths, and proof obligations

Use timing exceptions only when the functional contract justifies a different analysis edge—or proves that no legal capture edge exists at all.

Diagnose whether a failure comes from function, timing, constraints, or clock-domain assumptions and select a repair that remains safe in silicon.

Updated July 20261 connected chaptersInteractive labs + worked examples

Timing intent

An exception must describe function, not discomfort.

False paths and multicycle paths change what static timing analyzes. Both need an architectural proof. They are not interchangeable fixes for a difficult implementation path.

Analyzed edge window

No launch-to-capture timing check remains.

analysis disabled

False does not mean slow. It means no legal mode can sensitize the path, so neither setup nor hold has a meaningful capture edge.

Path does not functionally exist

False path

No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data.

Setup: Removed from setup analysis
Hold: Removed from hold analysis
Proof obligation: Prove the mutual exclusion, test mode, reset state, or configuration invariant that makes the path unreachable.
Source example: A test-mode and functional-mode mux pair whose select conditions are mutually exclusive, so no legal state can sensitize the complete path.

Conceptual SDC

set_false_path -from [get_pins src_reg/Q] \
  -to [get_pins dst_reg/D]

Showing False path. No legal operating mode can sensitize this launch-to-capture path. Static timing sees a graph edge, but the design contract says the edge can never carry sampled data. No setup or hold capture edge is analyzed.

Name the functional mode.

Reset, test, configuration, enables, and clock mode all matter.

Inspect the actual edges.

Read the timing report after the exception, including hold.

Prove the assumption.

Use assertions, formal reachability, or protocol verification.

Reasoning checkpoints

Questions worth answering without notes.

Each answer states the mechanism first, then the consequence.

01How is a false path different from a multicycle path?

A false path cannot be sensitized in the defined operating modes and is excluded from timing. A multicycle path is real and must work, but the design deliberately allows more than one clock cycle. Calling a slow real path false hides a functional timing failure.

Continue the system

Connect the adjacent layer.

Product intent to buildable machineSpecification to MicroarchitectureFollow one realistic DMA subsystem from an ambiguous product request to measurable requirements, executable interface contracts, a block architecture, and an evidence-ready handoff.Safe boundaries across time and voltageClock, Reset, CDC and PowerOperate a dual-clock, power-gated sensor subsystem from cold reset through configuration, streaming, quiesce, sleep, wake, and recovery while every crossing preserves meaning.RTL intent to signoff marginSynthesis and Timing ClosureAutopsy one failing register-to-register path as it moves from elaborated RTL to a mapped netlist, placed design, clock tree, extracted route, and signoff corner.