Logic and state
First decide whether the answer needs memory.
Digital logic becomes easier to reason about when every block has an explicit contract: transform current inputs, or sample and retain state. Timing then tells us whether that contract is physically achievable.
Combinational logic
y(t) = f(x(t))Output depends only on current inputs. There is no intentional state or sampling edge.
- Building blocks
- AND, OR, NOT, XOR, mux and FPGA LUT selection, decoder, encoder, adder, subtractor, comparator, and shifter
- Typical failure
- Incomplete assignment infers storage; deep logic creates setup pressure.
Sequential logic
Q(next) = f(Q(now), x)State changes at a defined event, normally a clock edge. Past history is represented by stored state.
- Building blocks
- Flip-flop, register, counter, shift register, finite-state machine, data pipeline, and memory interface
- Typical failure
- Unsynchronized inputs, reset-release hazards, and timing violations corrupt state.
Truth table, equation, state diagram, or cycle-level contract.
Combinational network plus the minimum intentional state.
Maximum delay for setup, minimum delay for hold, and CDC intent.
Simulation, assertions, lint, STA, CDC, and implementation checks.
Setup, hold, and register paths
A receiving register needs a quiet aperture.
Setup checks the latest arriving data before capture. Hold checks the earliest changing data after capture. They use different delay corners and require different fixes.
Setup time
The minimum interval that D must be stable before the active capture edge. A setup failure means the maximum data path arrives after the required time.
Intuition: have the input ready before the sampling buzzer.
Tperiod + Tskew ≥ tCQ(max) + Tcomb(max) + TsetupTypical repairs: pipeline, restructure HDL, reduce logic depth, use faster cells or higher synthesis effort, improve placement, or lengthen the period as a last resort.Hold time
The minimum interval that D must remain stable after the active capture edge. A hold failure means the minimum data path changes too early.
Intuition: keep the input still just after the sampling buzzer.
tCQ(min) + Tcomb(min) ≥ Thold + TskewTypical repairs: insert minimum-delay cells, detour routing, or reduce harmful skew. Frequency reduction does not help.Register timing boundaries
Data and clock race through different physical paths.
Interactive waveform
Select the data transition relative to the capture edge.
Data is stable on both sides of the sampling edge. The transition finishes before the setup window begins. The receiving register sees one unambiguous value for the complete aperture.
Register-to-register timing lab
Change the path and watch max and min timing separate.
Positive capture skew gives the setup path more time but makes the hold requirement harder in this simplified same-clock model.
Solve arrival time first, required time second, then compute slack = required − arrival.
Live arrival versus requirement
Slack is the distance between two labelled boundaries.
Required 1.88 ns − arrival 1.57 ns
Maximum path meets setup.Arrival 0.18 ns − required 0.14 ns
Minimum path meets hold.Setup slack 0.31 nanoseconds, passing. Hold slack 0.04 nanoseconds, passing.
Variation-aware timing
One path does not have one physical delay.
Process, voltage, temperature, local variation, crosstalk, and clock-tree behavior move launch, data, and capture delays differently. Signoff tests pessimistic combinations, not only a nominal waveform.
Slow launch clock-to-Q and data logic compete with an early capture clock edge. Maximum delay and frequency dominate.
Fast launch clock-to-Q and a short data path compete with a late capture edge. Minimum delay and skew dominate.
AOCV or POCV adjusts delay by path depth and variation. Common-path pessimism removal avoids charging the same shared clock segment as both early and late.