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Chapter 1 of 3 · Digital Design

Logic, state, setup, hold, and register paths

Decide whether behavior needs memory, then trace maximum- and minimum-delay paths through launch, transport, and the capture aperture.

Try the timing calculator Practice questions
Watercolor of an engineer’s notebook connecting a block diagram to a silicon package.

Logic and state

First decide whether the answer needs memory.

Digital logic becomes easier to reason about when every block has an explicit contract: transform current inputs, or sample and retain state. Timing then tells us whether that contract is physically achievable.

Combinational logic

y(t) = f(x(t))

Output depends only on current inputs. There is no intentional state or sampling edge.

Building blocks
AND, OR, NOT, XOR, mux and FPGA LUT selection, decoder, encoder, adder, subtractor, comparator, and shifter
Typical failure
Incomplete assignment infers storage; deep logic creates setup pressure.

Sequential logic

Q(next) = f(Q(now), x)

State changes at a defined event, normally a clock edge. Past history is represented by stored state.

Building blocks
Flip-flop, register, counter, shift register, finite-state machine, data pipeline, and memory interface
Typical failure
Unsynchronized inputs, reset-release hazards, and timing violations corrupt state.
1Specify

Truth table, equation, state diagram, or cycle-level contract.

2Implement

Combinational network plus the minimum intentional state.

3Time

Maximum delay for setup, minimum delay for hold, and CDC intent.

4Prove

Simulation, assertions, lint, STA, CDC, and implementation checks.

Setup, hold, and register paths

A receiving register needs a quiet aperture.

Setup checks the latest arriving data before capture. Hold checks the earliest changing data after capture. They use different delay corners and require different fixes.

Before the edge

Setup time

The minimum interval that D must be stable before the active capture edge. A setup failure means the maximum data path arrives after the required time.

Intuition: have the input ready before the sampling buzzer.

Tperiod + Tskew ≥ tCQ(max) + Tcomb(max) + TsetupTypical repairs: pipeline, restructure HDL, reduce logic depth, use faster cells or higher synthesis effort, improve placement, or lengthen the period as a last resort.
After the edge

Hold time

The minimum interval that D must remain stable after the active capture edge. A hold failure means the minimum data path changes too early.

Intuition: keep the input still just after the sampling buzzer.

tCQ(min) + Tcomb(min) ≥ Thold + TskewTypical repairs: insert minimum-delay cells, detour routing, or reduce harmful skew. Frequency reduction does not help.

Register timing boundaries

Data and clock race through different physical paths.

Clock pathData pathSetup boundaryHold boundary
Clock root · two branchesLaunch latency → FF_A
Capture latency → FF_B

Tskew = capture clock latency − launch clock latency

  1. FF_A · launch domainQ changes after tCQ.
  2. ↓ Logic + routeTcomb(max) / Tcomb(min) carries data to D.
  3. ↓ FF_B · capture domainFF_B samples D at the active edge.
MAX → setup
Latest arrival must precede capture − Tsetup.
MIN → hold
Earliest new data must arrive at or after capture + Thold.
Register-to-register setup and hold timing pathOne root clock travels to launch and capture registers with different latency. Data leaves the launch register after clock-to-Q, crosses combinational logic and routing, then must reach the capture register before setup and remain unchanged through hold. Clock skew is capture latency minus launch latency.LAUNCH DOMAINFF_AQ changes after tCQCAPTURE DOMAINFF_BD samples at active edgeLogic + routeTcomb(max) / Tcomb(min)tCQarrival at DTsetupTholdClock rootlaunch latencycapture latencyTskew = capture clock latency − launch clock latencyMAX → setupMIN → hold
Setup asks: can the latest data launched now arrive before the next capture edge minus Tsetup?Hold asks: can the earliest new data avoid contaminating the same capture edge through Thold?

Interactive waveform

Select the data transition relative to the capture edge.

  1. Before ↑ capture · SETUPD has already transitioned 0 → 1 and is stable.
  2. ↓ Active CLK edgeFF_B samples D.
  3. After ↑ capture · HOLDD remains stable after the capture edge.
Clock and data around one capture edgeThe purple region is the setup window before the capture edge. The amber region is the hold window after it. The selected data transition is at 214 on the time axis.CLKDSETUPHOLDcapture edge
Data is stable on both sides of the sampling edge.The transition finishes before the setup window begins. The receiving register sees one unambiguous value for the complete aperture.

Data is stable on both sides of the sampling edge. The transition finishes before the setup window begins. The receiving register sees one unambiguous value for the complete aperture.

Register-to-register timing lab

Change the path and watch max and min timing separate.

Positive capture skew gives the setup path more time but makes the hold requirement harder in this simplified same-clock model.

Solve arrival time first, required time second, then compute slack = required − arrival.

Live arrival versus requirement

Slack is the distance between two labelled boundaries.

All values in nanoseconds
Setup direction0.31 ns of max-path margin remains.Hold direction0.04 ns of min-path margin remains.
Setup slack0.31 ns

Required 1.88 ns − arrival 1.57 ns

Maximum path meets setup.
Hold slack0.04 ns

Arrival 0.18 ns − required 0.14 ns

Minimum path meets hold.

Setup slack 0.31 nanoseconds, passing. Hold slack 0.04 nanoseconds, passing.

Variation-aware timing

One path does not have one physical delay.

Process, voltage, temperature, local variation, crosstalk, and clock-tree behavior move launch, data, and capture delays differently. Signoff tests pessimistic combinations, not only a nominal waveform.

Setup cornerLate data, early capture

Slow launch clock-to-Q and data logic compete with an early capture clock edge. Maximum delay and frequency dominate.

Hold cornerEarly data, late capture

Fast launch clock-to-Q and a short data path compete with a late capture edge. Minimum delay and skew dominate.

OCV intuitionDerates model unequal variation

AOCV or POCV adjusts delay by path depth and variation. Common-path pessimism removal avoids charging the same shared clock segment as both early and late.

Check your understanding

Questions to reason through.

What is the practical difference between setup and hold?

Setup is a maximum-delay check: old-cycle data must reach the capture register before its active edge. Hold is a minimum-delay check: new-cycle data must not reach that register too soon after the edge. Setup is helped by a longer period or faster data path; hold usually needs added data delay or improved skew.

Put it into practice

Explain the decision behind the design.

Practice Digital Design in the question bank

Continue the learning path

Next: Timing intent

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