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DescriptionQ060
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Q060DVASIC interview problem

Reset Pulse Is Too Short

TechniquesDVWaveform DebuggingReset
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

reset_n is an active-low synchronous reset. It is sampled only on rising edges where clk_enable=1; clk_enable is 1 on every displayed edge. Rule to apply: When reset_n falls on an enabled edge, it must be sampled low on at least two consecutive enabled edges, including the fall edge as the first one. Which reset-width assertion fails on this waveform?

Waveform for Reset Pulse Is Too Short. Signals: reset_n, state_valid, clk_enable. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)