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DescriptionQ010
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Q010DVASIC interview problem

Unknown Output After Reset

TechniquesDVWaveform DebuggingReset
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. reset_n is the top-level active-low reset; both displayed output registers are still unknown on the first edge after release. Rule to apply: The local reset out_reset_n must clear out_valid to 0 and out_data to 0x00. The top-level and local reset paths may differ. Which signal should be traced next to check whether reset reached the output registers?

Waveform for Unknown Output After Reset. Signals: reset_n, out_valid, out_data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)