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DescriptionQ165
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Q165DVASIC interview problem

Block Remains in Reset

TechniquesDVWaveform DebuggingCDCReset
DifficultyEasy
TopicWaveform Debugging
LanguageSystemVerilog
Format4 choices
01

Problem

Each column is one rising clock edge. The top-level reset is released at C2, but block_active remains low through C7 after local synchronization time. Rule to apply: Top-level reset release must reach block_reset_n_sync within two sampled edges. While block_enable=1, block_active must become 1 on the following edge. Therefore a C2 top-level release makes C5 the latest legal block_active assertion. Which signal should be traced next to find out whether reset release reached the block?

Waveform for Block Remains in Reset. Signals: reset_n, block_enable, block_active. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
02

Answer choices (4)