Skip to SystemVerilog OOP questions

SystemVerilog OOP interview preparation

Everything you need to refresh about SystemVerilog object-oriented programming: classes, constructors, inheritance, polymorphism, virtual methods, $cast(), copying, and reusable design verification patterns before a DV interview.

SystemVerilog class model and visibilityKnow what the handle actually owns.

Start with the SystemVerilog object model, the four OOP ideas, and the visibility rules that keep verification classes reusable without exposing mutable internals.

Concept model

A class defines behavior; handles reach objects

Type definitionOne class, many objects
blueprintclass Packet
  • addrproperty
  • dataproperty
  • format()method
handlepkt_aaddr = 10
handlepkt_baddr = 42
handlepkt_caddr = 91
Encapsulation boundaryVisibility follows the caller
unqualifiedclasschildoutside
protectedclasschildoutside
localclasschildoutside

The class is one type definition. Each new allocation creates a distinct object, while handle assignment can make multiple names refer to the same object.

Strong answer

A class is a type definition. An object is one allocated instance of that class. A class variable stores a handle that is either null or refers to an object; the handle is not the object itself.

Reason it through

  • Declaring Packet p creates a handle initialized to null. Executing p = new allocates a Packet object and places its handle in p.
  • Two different calls to new create two independent objects. Assigning one handle to another creates an alias to the same object.
  • Methods execute against the object reached through the handle, so a null-handle dereference is a runtime error.
Type, allocation, and aliasingsystemverilog
class Packet;
  int id;
endclass

Packet p;        // null handle
Packet alias_p;

p = new;         // allocate one Packet object
p.id = 7;
alias_p = p;     // same object, second handle
alias_p.id = 9;  // p.id is now 9

SystemVerilog construction and specializationInitialize the hierarchy in order.

Reason about new(), base-constructor chaining, this and super, parameterized class types, and state shared at class scope.

Concept model

Construction flows from base state to specialization

Constructor orderBuild the base before the child
01allocateDerived objectproperties receive defaults
02super.new(args)Base constructorestablish inherited state
03this.tag = tagDerived constructorfinish specialized state
Compile-time specializationOne template, explicit types
class templatePacket #(WIDTH, T)
WIDTH = 64value parameterT = bit[15:0]type parameter
specialized typePacket #(64, bit[15:0])

A derived constructor establishes inherited state before its own fields. Value and type parameters specialize the class at compile time rather than at object creation.

SystemVerilog inheritance and dispatchSeparate handle type from object type.

Trace virtual calls, non-virtual hiding, super calls, static method resolution, and the constructor-time dispatch trap without guessing from the variable name.

Concept model

The virtual keyword changes the lookup path

Runtime dispatchThe base declaration marked the method virtual, so the object's dynamic type selects the implementation.

Virtual calls follow the dynamic object type. Non-virtual and static calls are bound from the declared type or class scope, even when the handle refers to a derived object.

SystemVerilog abstract types and castingProgram to a contract you can check.

Use virtual classes and pure virtual methods to define incomplete base types, then move through the hierarchy with safe upcasts and checked downcasts.

Concept model

Abstract bases define the contract boundary

Abstract contractDeclare the promise once
cannot instantiatevirtual class Shapepure virtual function area()
concrete childRectarea() implemented
concrete childCirclearea() implemented
Handle conversionUpcast freely; check the way down
Rect handleShape handleupcast · always safe
Shape handleRect handle$cast() · runtime check

A concrete child must satisfy every inherited pure virtual contract. Upcasting preserves the object behind a base handle; $cast() verifies a downcast at runtime.

SystemVerilog copying and ownershipDraw the handle graph before copying.

Distinguish handle assignment, built-in shallow object copy, explicit deep copy, shared configuration, and object lifetime so nested state cannot alias by accident.

Concept model

Copy values deliberately; do not copy aliases blindly

Alias riskScalar fields are copied, but nested class handles still reach the same objects.

A shallow copy duplicates scalar members but preserves nested handles. A deep copy allocates every owned child object and then copies its value.

SystemVerilog OOP in design verificationKeep components stable as transactions evolve.

Apply polymorphic transactions, factories, singletons, and inherited constraints to verification architectures without turning every extension into a component rewrite.

Concept model

Base handles let new packet types reuse old components

Verification architectureKeep components generic
derived objectread_packet
derived objectwrite_packet
stored aspacket handle
unchanged componentdriverpkt.display()
unchanged componentmonitorpkt.format()
Inherited constraintsNames decide layer or replace
different namesbase_c + child_cboth active · intersect
same namebase_cbase_cderived block replaces base

Drivers and monitors can accept a base transaction handle while virtual methods preserve type-specific behavior. Constraint block names decide whether inherited rules layer or replace.