1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ805

Q805DVDesignASIC interview problem

Build a reset-responsive nonblocking driver

TechniquesUVMDriverResettry_next_item

DifficultyHard

TopicUVM Components

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Implement a clock-responsive ready/valid driver that uses try_next_item(), immediately idles during reset, waits one clean cycle after reset release, and retries an interrupted item.

Example input and output

Use this case to check your interpretation

Input

item A is presented but reset asserts before handshake; reset releases; one full clean cycle passes; ready then accepts A

Output

pins idle throughout reset and release cycle; A is retried unchanged and item_done occurs once after acceptance

Explanation

Reset aborts only the pin-level attempt, while the buffered sequence item remains owned for a post-reset retry.

Requirements (4)

The main loop must keep observing reset even when no sequence is active.
Reset aborts the pin-level attempt but preserves the buffered item for retry.
Drive a known idle state throughout reset and for one complete release cycle.
Complete the sequence item only after its post-reset handshake.