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DescriptionQ1041
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Q1041DesignBroadcomASIC interview problem

Effect of positive capture-clock skew

TechniquesDesignSTATimingEffectskew
DifficultyEasy
TopicTiming & STA
LanguageSystemVerilog
Format4 choices
01

Problem

For one register-to-register path, the capture clock arrives later than the launch clock. All other delays are unchanged. What is the usual first-order timing effect of this positive capture skew?

02

Answer choices (4)